Abstract: A structure including at least two neighboring components, capable of operating at high frequencies, formed in a thin silicon substrate extending on a silicon support and separated therefrom by an insulating layer, the components being laterally separated by insulating regions. The silicon support has, at least in the vicinity of its portion in contact with the insulating layer, a resistivity greater than or equal to 1,000 ohms.cm.

Abstract: A method for protecting an integrated circuit. According to the method, the start-up of all, or part, of the circuit is determined in the presence of a key which is recorded in a non-volatile manner in the circuit, following the production thereof, and depends on at least one first parameter which is present in a non-volatile manner in the circuit after the production thereof.

Abstract: A method for controlling a piezoelectric motor, such that control signals of the motor are periodic non-sinusoidal voltage signals.

Abstract: A method and device for encrypting and/or decrypting binary data blocks protecting both confidentiality and integrity of data sent to or received from a memory. The encryption method comprises steps of: applying to the input data block a reversible scrambling process, the scrambling process providing a scrambled data block in which the bits of the input data block are mixed so that a modification of one bit in the scrambled data block impacts on every bit of the input data block, and applying to the scrambled data block a stream cipher encryption algorithm providing an encrypted data block. Application can be made to secured integrated circuits requiring to securely store data in an external memory.

Abstract: The invention relates to a method and device for the irreversible reduction of the value of an integrated polycrystalline silicon resistor. The inventive method consists in temporarily subjecting the resistor to a stress current which is greater than a current (Im) for which the value of the resistor is maximum.

Abstract: A receiver of a frequency-modulated signal representing a digital signal includes a down conversion unit or frequency translation unit to lower the frequency of the frequency-modulated signal and a digital demodulator to regenerate the digital signal from the lowered-frequency signal. The receiver furthermore includes a counter circuit to determine the number of periods of a reference signal from the frequency translation unit during a period of the lowered-frequency signal. The digital demodulator includes a computer unit to compute the period of the lowered-frequency signal from the number of periods of the reference signal.

Abstract: A logic circuit comprises a logic module comprising a functional synchronous flip-flop receiving a functional result comprising several bits in parallel, and supplying a synchronous result. A module for checking the integrity of the functional flip-flop comprises a first coding block receiving the functional result and supplying a first code, a second coding block receiving the synchronous result and supplying a second code, a checking synchronous flip-flop receiving the first code and supplying a third code, and a comparator for comparing the second code with the third code and for supplying a first error signal.

Abstract: A dynamic random access memory circuit including a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of the memory plane corresponding to a page of words. Two buffer registers are coupled with the memory plane for reading words in a page of the memory and for writing new words to a page of the memory, and the registers are used alternatively to access this memory plane. The buffer registers are dual-port memories and, moreover, the memory has an error correcting circuit allowing read-modify-write cycles applied to a group of n words within the same page. Whereby the reliability of the memory circuit is substantially increased and, moreover, an alternative solution to burn-in can even be offered. The invention also provides a method for controlling a dynamic memory having an error correcting code mechanism.

Abstract: A method is provided for secured transfer of an N-byte data element from a first memory containing the data element to a second memory through a data bus that is connected between the first memory and the second memory. According to the method, a transfer rule is defined with at least one parameter whose value is chosen at random before each transfer of the data element. The N-byte data element is transferred byte-by-byte through the data bus in accordance with the transfer rule, with each byte transition once and only once through the data bus. In a preferred method, the transfer rule is a permutation of the bytes of the N-byte data element. Also provided is a programmable circuit having a random number generator that supplies at least one parameter of a data transfer rule.

Abstract: A method for providing a context datum associated with a source and/or destination device based on an address datum associated with the device, including addressing, based on the address datum, a unit for providing an index, the unit containing, for each address datum, an indicator indicating whether the device is active; and addressing, based on the index provided by the unit, a context memory for providing the context datum associated with the device.

Abstract: An electrical connection device includes a platform and a moving head. Between these components a semiconductor component is received and retained. The semiconductor component includes an electrical connection plate bearing an integrated circuit chip. The platform supports the making of electrical connection with front electrical connection terminals provided on a front panel of the electrical connection plate. The moving head bears a printed circuit board having interlinked pairs of contact terminals and associated pairs of electrical connection posts which make contact between the pairs of contact terminals of the printed circuit board and rear link terminals and rear transfer terminals provided on a rear panel of the electrical connection plate. The electrical connection plate includes circuitry which electrically connects the rear link terminals to the chip and also circuitry which electrically connects rear transfer terminals to front transfer terminals.

Abstract: A device includes a processor (1) having two states (111, 112) each storing a processing path, a central unit (11) processing the paths in those states, at least one transfer bus (13) between the processor and peripherals, at least one processing path backup and restore bus (14), distinct from the data bus, and a backup and restore memory (15). A processing path controller (16) controls the transfer of a processing path between the memory and a state while the processor processes the processing path of another state. This allows for a reduction in the time wasted by the controller on restore or backup transfers.

Abstract: A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.

Abstract: An integrated circuit includes many metallization levels. A thick dielectric region is placed above at least two metallization levels and laterally neighboring two or more metallization levels. That part of the two metallization levels which lie beneath the dielectric region forms a screen. A conducting strip is placed on the dielectric region so that the dielectric region forms a waveguide.

Abstract: A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma including, in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.

Abstract: An image sensor including a pixel assembly, each pixel including a photodiode and an access transistor connected to a read circuit, the photodiode and the access transistor being formed in and above a first semiconductor substrate, all or part of the read circuit being formed in a second semiconductor substrate, the second substrate being placed above the first substrate and separated therefrom by an intermediary insulating layer covering the access transistor, the photodiode receiving incident photons on its lower surface side opposite to the intermediary insulating layer.

Abstract: The invention concerns a method for locating, in a digital image, a circle centre comprising the following steps: a) predefining a set of potential radii of the circle; b) dimensioning (303) two accumulators to a dimension in the form of a column matrix not larger than the size of the image in x-axis and a line matrix not larger than the size of the image in y-axis; c) sequentially, for each pixel image of the image: (i) selecting successively each potential radius; (ii) evaluating the position of the potential center of a circle of the selected radius and whereof the pixel concerned is on the periphery; and (iii) incrementing accumulators at the x-axis and the y axis of the potential center; and d) selecting (304) as coordinates of the located centre, the x-axis and the y-axis corresponding to the maximum of accumulators.

Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.

Abstract: An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N configurable cells are coupled by their functional input and their output to logic blocks with which they cooperate to form at least one logic circuit. The disclosed circuit also includes a test mode in which the N configurable cells are coupled by their propagation input and their output to the logic blocks and in which the output of the Nth configurable cell is coupled to a functional input of the first logic block to form an oscillator.

Abstract: An electrically erasable and programmable memory in which control gate transistors have been suppressed includes memory cells each with an access transistor and a floating gate transistor. A word line decoder is connected to word lines of the memory cells by a selection line connected to the gate terminals of the access transistors of the word line, and by a control gate line connected to the control gates of the floating gate transistors of the word line. Thus the voltage applicable to the gate terminals of the floating gate transistors is no longer limited by the voltage susceptible of being obtained on the source terminal of the control gate transistors.