Abstract: A MOS transistor capable of withstanding significant currents, having doped areas corresponding to first and second main terminals of elementary MOS transistors and having, in top view, the shape of parallel strips separated by gate regions; first conductive elements which do not extend on the doped areas corresponding to the second main terminals and dividing into first fingers extending at least partly on the doped areas corresponding to the first main terminals and connected thereto; and second conductive elements which do not extend on the doped areas corresponding to the first main terminals and divide into second fingers extending at least partly on the doped areas corresponding to the second main terminals and connected thereto, the second fingers being at least partly intercalated with the first fingers.
Type:
Application
Filed:
December 26, 2007
Publication date:
July 3, 2008
Applicant:
STMicroelectronics S.A.
Inventors:
Sandrine Majcherczak, Carlo Tinella, Olivier Richard, Andreia Cathelin
Abstract: A method and a system for transferring a digital signal through a transformer, in which the current in a primary winding of the transformer is a frequency-modulated signal exhibiting sinusoidal trains of different durations according to the rising or falling edge of the digital signal to be transferred.
Abstract: A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for detecting that a first instruction intended for a first area is a predetermined instruction to be followed by a period during which the first area can receive no other instruction, and third circuitry for, during the period, providing instructions to another memory area.
Type:
Grant
Filed:
June 2, 2006
Date of Patent:
July 1, 2008
Assignee:
STMicroelectronics S.A.
Inventors:
Pierre Marty, Gaelle Rey, Pascal Chauvet
Abstract: A coupler of distributed type including a first conductive line carrying a main signal between two end terminals, a second conductive line coupled to the first one and between two terminals of which flows a sampled signal, proportional to the main signal, and two capacitors respectively connecting the two terminals of each of the lines.
Abstract: A resistor formed in a semiconductor substrate of a first conductivity type comprising parallel trenches, the resistor being formed of a layer of the second conductivity type extending on two opposite walls and the bottom of at least one trench.
Abstract: A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.
Type:
Application
Filed:
December 18, 2007
Publication date:
June 26, 2008
Applicant:
STMicroelectronics S.A.
Inventors:
Stephan Courcambeck, Albert Martinez, Jean Nicolai, William Orlando
Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.
Abstract: A memory is organized with many memory subspaces (db<i>) each including their own read-out circuit (SA<i>). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory via a write bus (TD) and a read bus (Q). The memory controller generates a signal (TD<i>) for enabling the redundant column. This signal is provided so as to be conveyed to the read-out circuits of the memory to which the write bus (TD) is connected. Thus, one enables, via the read-out circuits, the redundant column of the memory subspaces which are associated with a defective column address.
Abstract: For each current image output from a pixel matrix, the digital words relative to at least one masked line of the matrix are processed to generate a current correction digital code. From this code, a black level compensation signal is generated and applied as an offset control on pixel signal amplification. If the current correct digital code does not differ from the code calculated for a previous image output by a predetermined amount, then the code for the previous image is instead used to generate the black level compensation signal.
Abstract: A support 7 for an acoustic resonator 4 includes at least one bilayer assembly having a layer of high acoustic impedance material 11 and a layer of low acoustic impedance material 12 made of material having a low electrical permittivity.
Abstract: An acoustic resonator assembly includes a layer of high-acoustic-impedance material and a layer of low-acoustic-impedance material made of a low-electrical-permittivity material. This assembly may support the resonator over an interconnect layer or act as a decoupling assembly between two active elements of the resonator. The assembly may alternatively include three low-acoustic impedance layers. Alternatively, the assembly may include three acoustic impedance layers wherein two of the layers are low acoustic impedance layers and the third layer has a higher acoustic impedance than the first two or alternatively is a high-acoustic impedance layer.
Abstract: An optical unit including a glass substrate supporting a diaphragm intended to receive a lens with a circular base, the surface of the diaphragm having one or several protruding elements for guiding the lens in horizontal positioning, and its manufacturing method.
Abstract: A dedicated processing module includes an input for data to be processed and an output for processed data. A block input and a block output are also included. A processing component for the module performs a digital processing operation on the data present at the data input and applies the processed data at the data output. The processor may further generate a block request. A control device within the module reproduces, at the block output, a block request applied to the block input or generated by the processing component. The control device thus may operate to block the application of processed data at the data output upon receipt of a block request at the block input. Two or more dedicated processing modules may be connected in series with each other to form a processing flow chain with the data output of one module connected to the data input of a subsequent module. Additionally, the block output of the subsequent module is connected to the block input of the preceding module.
Abstract: A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improves the overall dielectric constant of the resulting dielectric element.
Abstract: A voltage-controlled vertical bidirectional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch.
Abstract: A switch for switching video signals in a set top box between a first interface for connecting the set top box to a television, a second interface for connecting the set top box to a video playback device, and decoding circuitry for decoding a video stream, the set top box including a processor having a low power mode in which the decoding circuitry is inactive, the switch including detection circuitry arranged to detect, while the processor is in the low power mode, activity on a video input line of one of the first and second interfaces, and arranged to output an activation signal to switching circuitry in the switch to activate a loop through between the first and second interfaces when activity is detected.
Abstract: A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.
Type:
Application
Filed:
December 5, 2007
Publication date:
June 19, 2008
Applicant:
STMicroelectronics S.A.
Inventors:
Sebastien Barasinski, Francois Jacquet, Marc Sabut
Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.
Type:
Grant
Filed:
June 13, 2006
Date of Patent:
June 17, 2008
Assignee:
STMicroelectronics S.A.
Inventors:
Sylvie Wuidart, Mathieu Lisart, Nicolas Demange
Abstract: A circuit generates a reference voltage that is independent of temperature. The circuit is built on a substrate according to a CMOS technology, and includes a first stage for generating a first current proportional to temperature and a second stage for generating a second current inversely proportional to temperature. These first and second currents are summed in a resistor connected to a voltage distinct from the ground of the first and second stages and formed by the voltage of the substrate on which the circuit is built.