Patents Assigned to STMicroelectronic S.A.
  • Publication number: 20080137430
    Abstract: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.
    Type: Application
    Filed: February 19, 2008
    Publication date: June 12, 2008
    Applicant: STMicroelectronics S.A.
    Inventor: Jean Lasseuguette
  • Patent number: 7385254
    Abstract: A structure of protection of a first area of a semiconductor wafer including a substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer, includes a very heavily-doped wall of the first conductivity type having substantially the depth of the upper portion. The wall is divided into three heavily-doped strips of the first conductivity type separated and surrounded by medium-doped intermediary strips of the first conductivity type. The distance between the heavily-doped strips being of the order of magnitude of the substrate thickness.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: June 10, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Didier Belot
  • Publication number: 20080129262
    Abstract: A switching power supply source including an inductance with first and second terminals; an output node; an NMos transistor, the drain of which is connected to the first terminal; a PMos transistor, the drain of which is connected to the first terminal; a control device generating control signals for NMos and PMos transistors assuring that these transistors are not conducting simultaneously; a capacitor with a third terminal connected to the first terminal and a fourth terminal; a resistance with a fifth terminal connected to the fourth terminal and a sixth terminal; and an NMos transistor the drain of which is connected to the grid of the PMos transistor and the gate of which is connected to the fourth terminal.
    Type: Application
    Filed: February 5, 2008
    Publication date: June 5, 2008
    Applicant: STMicroelectronics S.A.
    Inventors: Alexandre Balmefrezol, Jean-Luc Patry
  • Patent number: 7382902
    Abstract: A method and a system for evaluating the definition of the image of an eye iris or the like, including approximately localizing the pupil in the image, defining, from the approximate position of the pupil, an examination window centered on this position, and applying a gradient accumulation operation to the luminance values of the pixels of the examination window, the running total being proportional to the definition score of the image.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: June 3, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Christel-Loïc Tisse, Laurent Plaza, Guillaume Petitjean
  • Patent number: 7382174
    Abstract: A transconductor including circuitry for automatically selecting a non-linear class A operation or a linear class AB operation based on an input signal to be processed to generate an output signal, and for automatically adjusting current from a power supply to a level needed for operation of the transconductor.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: June 3, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Belot, Pascal Persechini
  • Patent number: 7381267
    Abstract: A method for forming, by epitaxy, a heteroatomic single-crystal semiconductor layer on a single-crystal semiconductor wafer, the crystal lattices of the layer and of the wafer being different, including forming, before the epitaxy, in the wafer surface, at least one ring of discontinuities around a useful region.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: June 3, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Daniel Bensahel, Olivier Kermarrec, Yves Morand, Yves Campidelli, Vincent Cosnier
  • Publication number: 20080122743
    Abstract: A device for controlling a matrix screen includes a scanning circuit. The scanning circuit includes a row control block which successively selects each row, and a column control block which, for each selected row, selects or deselects a set of columns of the screen with the aid of column selection or deselection signals. The temporal evolution of each column selection signal and of each column deselection signal includes a first and a second part separated by an intermediate porch. The column control block, for each column of the screen, determines if the corresponding column has to be selected or deselected, determines the value of the capacitance seen by the column termed the column-capacitance, and adjusts temporal evolution characteristics of the selection or deselection signal of at least one column to be selected or deselected as a function of the determined value of its column-capacitance.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Applicant: STMicroelectronics S.A.
    Inventors: Jean-Raphael Bezal, Eric Cirot
  • Patent number: 7379512
    Abstract: A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: May 27, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Marc Joisson, Luc Garcia, Marc Gens
  • Patent number: 7375583
    Abstract: A differential biquad filter includes positive and negative single ended circuits connected between first and second power supply terminals. Each single ended circuit includes a single input terminal; a transistor having a control terminal, and first and second main terminals; a single output terminal corresponding to the control terminal of the transistor; first and second conductances connected between the single input terminal and the control terminal of the transistor; a first capacitance connected between the control terminal of the transistor and the second main terminal of the other single ended circuit; and a second capacitance connected between the node between the first and second conductances on one hand and the second main terminal of the transistor on the other hand. The differential biquad filter also includes a fifth capacitance connected between the second main terminals of each transistor of each single ended circuit.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: May 20, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Eoin Ohannaidh
  • Patent number: 7375603
    Abstract: A non-directional coupler including a semiconductor junction in series with a capacitor, the semiconductor junction being formed so that the threshold frequency short of which it behaves as a rectifier is smaller than the coupler's operating frequency.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: May 20, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: François Dupont, Patrick Poveda
  • Patent number: 7375502
    Abstract: A method and a circuit for scrambling the current signature of a load comprising at least one integrated circuit executing digital processings, including supplying at least the integrated circuit from a supply voltage external to the circuit by combining a current provided by a first linear regulator with a current provided by at least one capacitive switched-mode power supply circuit with one or several switched capacitances.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: May 20, 2008
    Assignees: STMicroelectronics S.A., Universite D.Aix-Marseille I
    Inventors: Alexandre Malherbe, Edith Kussener, Vincent Telandro
  • Patent number: 7372728
    Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: May 13, 2008
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.
    Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel
  • Patent number: 7373463
    Abstract: An integrated circuit and an antifraud method implementing at least one operation involving at least one secret quantity, and functionally including upstream and downstream of the operator at least one source register and at least one destination register, respectively, and including means for loading a random number at least in the destination register.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: May 13, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Yannick Teglia, Pierre-Yvan Liardet
  • Patent number: 7372965
    Abstract: The invention proposes a method of managing an electronic circuit of the type comprising a memory (EEPROM) for the storage of confidential information, the method comprising masking variations of the electrical current (I) consumed by the electronic circuit, during a fraction of the time only (ti-tj), at least during the portion(s) of time during which an instruction bearing on confidential data is executed, and notably an instruction for reading out from the memory (EEPROM).
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: May 13, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Sylvie Wuidart
  • Patent number: 7372359
    Abstract: An electromagnetic transponder including: a parallel oscillating circuit adapted to extracting a supply signal from a radiated field; in parallel with the oscillating circuit, several branches each including a programmable resistor and a switch; and a cyclic control element for successively turning on the switches, each resistor forming an element for storing a portion of the code stored in the transponder.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: May 13, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Luc Wuidart, Michel Bardouillet
  • Patent number: 7372304
    Abstract: An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: May 13, 2008
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.
    Inventors: Serge F. Fruhauf, Alain C. Pomet
  • Patent number: 7372337
    Abstract: The present invention relates to a method for stabilising the operation of a voltage controlled oscillator driven by a phase locked loop, the voltage controlled oscillator delivering an RF signal and receiving through at least one spurious path a harmonic component of a frequency equal or proximate to that of the RF signal, capable of disturbing its operation by injection pulling. According to the present invention, the method comprises a step of injecting into the voltage controlled oscillator an injection pulling compensation signal, the phase and the amplitude of which are adjusted so as to neutralise the effects of the spurious harmonic component. Application particularly to phase modulation IQ circuits in radiotelephony.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 13, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Peter Nayler
  • Patent number: 7372290
    Abstract: A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided by at least one of the registers. The combinatorial logic is also capable of performing one or more combinatorial operations using the at least one received output value. In addition, the secure microcontroller includes dummy cycle circuitry capable of causing one or more of the registers and the combinatorial logic to change state and consume current during one or more dummy cycles.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: May 13, 2008
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.
    Inventors: Serge F. Fruhauf, Alain C. Pomet
  • Patent number: 7370264
    Abstract: A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns wherein; a first column is a complement of a second column; the value of the second column ranges from 9 to 271 in increments of two; a third column is a complement of a fourth column; and the value of the fourth column is the same as the value of the second column less one; and wherein a 528-bit bottom row is added to the 10×528 matrix comprising alternating zeroes and ones starting with a zero creating an 11×528 matrix.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: May 6, 2008
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.
    Inventors: James Leon Worley, Laurent Murillo
  • Patent number: 7369614
    Abstract: A circuit for controlling an MPEG decoder rated by a signal of given period likely to decode several coded images, receiving at each period beginning an order to decode several images of a first or of a second type, the images of the second type being decodable at any instant of the period following their decoding order, and the images of the first type being decodable at any instant of the two periods following their decoding order, including a priority assignment circuit for, at each period, granting among these images the decoding priority, if there are any, to the images of the first type that still have not been decoded one period after their decoding order and otherwise, if there are any, to the images of the second type.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: May 6, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Michel Moutin