Patents Assigned to STMicroelectronic S.r.l.
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Publication number: 20230369279Abstract: A semiconductor die is attached on a die-attachment portion of a planar substrate. A planar electrically conductive clip in mounted onto the semiconductor die. The semiconductor die is sandwiched between the die-attachment portion and the electrically conductive clip. A distal portion of the electrically conductive clip extending away from the semiconductor die is spaced from an electrically conductive lead of the planar substrate by a gap. This gap is filled by a mass of gap-filling material transferred to an upper surface of the electrically conductive lead via Laser Induced Forward Transfer (LIFT) processing. A mass of the gap-filling material is sized and dimensioned to substantially fill the gap.Type: ApplicationFiled: May 8, 2023Publication date: November 16, 2023Applicant: STMicroelectronics S.r.l.Inventors: Thomas GOTTARDI, Nicoletta MODARELLI, Guendalina CATALANO
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Publication number: 20230370056Abstract: An HS switching transistor is coupled between a high-side node and a switching node. An LS switching transistor is coupled between the switching node and a low-side node. An inductive load is coupled to the switching node in a way where one of the HS/LS switching transistors is freewheeling. In response to detection of a short circuit occurring at the switching node with the freewheeling switching transistor in the conductive state: an electrical signal at the switching node is sensed, a comparison is made between the sensed electrical signal and a threshold level, and a driving signal is provided to control freewheeling switching transistor to switch to the non-conductive state when the comparison indicates that the electrical signal has reached the threshold level.Type: ApplicationFiled: May 8, 2023Publication date: November 16, 2023Applicant: STMicroelectronics S.r.l.Inventors: Vanni POLETTO, Fabrizio LOI
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Patent number: 11817838Abstract: An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.Type: GrantFiled: March 4, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics S.r.l.Inventors: Calogero Marco Ippolito, Michele Vaiana
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Patent number: 11817791Abstract: A synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. A second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and a third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant in which the measured voltage reaches a first threshold value and a switch-off instant in which the measured voltage reaches a second threshold value. The synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal as a function of the measured voltage.Type: GrantFiled: September 30, 2021Date of Patent: November 14, 2023Assignees: STMicroelectronics S.r.l., STMicroelectronics Design and Application S.R.O.Inventors: Alberto Iorio, Maurizio Foresta, Emilio Volpi, Jan Novotny
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Patent number: 11817864Abstract: In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the referType: GrantFiled: June 14, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics S.r.l.Inventors: Luigi Sole, Antonio Giordano
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Publication number: 20230360927Abstract: A semiconductor integrated circuit chip is arranged on a first surface of a substrate that includes electrically conductive lead formations in an array, wherein the electrically conductive lead formations are covered by a masking layer at a second surface opposite the first surface. The semiconductor integrated circuit chip is electrically coupled to electrically conductive lead formations and an insulating encapsulation is molded on the semiconductor integrated circuit chip. The masking layer is then selectively removed, for example, via laser ablation, from one or more of the electrically conductive lead formations. The electrically conductive lead formations that are left uncovered by the masking layer are then removed by an etching process applied to the second surface of the substrate. The selective removal of the unmasked electrically conductive lead formations serves to increase a creepage distance between those conductive lead formations that are left in place.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMicroelectronics S.r.l.Inventor: Fulvio Vittorio FONTANA
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Publication number: 20230361010Abstract: A semiconductor chip or die is arranged on a first surface of a thermally conductive die pad of a substrate such as a leadframe. An encapsulation of insulating material in molded onto the die pad having the semiconductor die arranged on the first surface. At the second surface of the die pad, opposite the first surface, the encapsulation borders on the die pad at a borderline around the die pad. A recessed portion of the encapsulation is provided, for example, via laser ablation, at the borderline around the die pad. Thermally conductive material such as metal material is filled in the recessed portion of the encapsulation around the die pad. The surface area of the thermally conductive die pad is augmented by the filling of thermally conductive material in the recessed portion of the encapsulation thus improving thermal performance of the device.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMicroelectronics S.r.l.Inventor: Riccardo VILLA
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Publication number: 20230360928Abstract: A semiconductor die is attached on a die mounting surface of a substrate. An insulating encapsulation of laser direct structuring (LDS) material is molded onto the substrate and the semiconductor die. The insulating encapsulation of LDS material has a front surface including a first portion and a second portion separated by gaps therebetween. Laser direct structuring processing is applied to the first portion of the front surface to structure in the encapsulation of LDS material electrically conductive formations including electrically conductive lines over the front surface and to the second portion of the front surface of the encapsulation of LDS material to form thereon a reinforcing warp-countering structure. The separation gaps are left exempt from laser direct structuring processing and the reinforcing warp-countering structure is electrically insulated from the electrically conductive lines by LDS material left exempt from laser direct structuring processing at the separation gaps.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMicroelectronics S.r.l.Inventors: Marco ROVITTO, Dario VITELLO
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Patent number: 11809740Abstract: A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.Type: GrantFiled: May 18, 2022Date of Patent: November 7, 2023Assignee: STMicroelectronics S.r.l.Inventor: Walter Girardi
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Patent number: 11808650Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.Type: GrantFiled: October 5, 2020Date of Patent: November 7, 2023Assignee: STMicroelectronics S.r.l.Inventors: Alberto Pagani, Federico Giovanni Ziglioli, Bruno Murari
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Patent number: 11811298Abstract: A sensor circuit for a power FET monitors current flowing through the FET and includes a regulator circuit regulating a first current flowing through a sense resistance, so voltage drop at the sense resistance corresponds to voltage drop between terminals of the FET. A measurement circuit provides a second current corresponding (or being proportional) to the first current. A first switch selectively applies the second current to a resistor based on a first control signal, and a low pass filter generates a low-pass filtered signal by filtering voltage at the resistor. A voltage follower generates a replica of the low-pass filtered signal, and a second switch selectively applies the replica to the resistor. When the FET is closed, a control circuit closes the first switch and opens the second electronic switch. When the FET is opened, the control circuit opens the first electronic switch and closes the second electronic switch.Type: GrantFiled: November 23, 2021Date of Patent: November 7, 2023Assignee: STMicroelectronics S.r.l.Inventors: Stefano Ramorini, Roberto Pio Baorda
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Patent number: 11808063Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.Type: GrantFiled: March 3, 2023Date of Patent: November 7, 2023Assignees: STMicroelectronics S.r.l., STMicroelectronics, Inc.Inventors: Williamson Sy, Emiliano Mario Piccinelli, Keith Walters
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Patent number: 11808837Abstract: A method of operating a radar sensor system includes: frequency down-converting a reception signal that is chirp-modulated with a sequence of chirp ramps to an intermediate frequency signal; and high-pass filtering the intermediate frequency signal to produce a high-pass filtered signal. High-pass filtering includes: first high-pass filtering, with a first corner frequency, the intermediate frequency signal at each chirp in the chirp modulation of the reception signal; and replacing the first high-pass filtering with a second high-pass filtering with a second corner frequency, the first corner frequency being higher than the second corner frequency.Type: GrantFiled: December 6, 2021Date of Patent: November 7, 2023Assignee: STMicroelectronics S.r.l.Inventors: Francesco Belfiore, Salvatore Scaccianoce, Amedeo Michelin Salomon, Antonino Calcagno
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Publication number: 20230348258Abstract: MEMS structure, comprising: a semiconductor body; a cavity buried in the semiconductor body; a membrane suspended on the cavity; and at least one antistiction bump completely contained in the cavity with the function of preventing the side of the membrane internal to the cavity from sticking to the opposite side, which delimits the cavity downwardly.Type: ApplicationFiled: April 18, 2023Publication date: November 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Mikel AZPEITIA URQUIA, Enri DUQI, Silvia NICOLI, Roberto CAMPEDELLI, Igor VARISCO, Lorenzo TENTORI
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Publication number: 20230353053Abstract: A multiphase DC-DC converter has two converter arrangements, each with a switching stage that has a switching node, an inductor, a converter output node, a high-side switch, and a low-side switch. Current sensing circuits detect the instantaneous current flowing through either the high-side or low-side switches, and signal time-averaging circuits produce time-averaged signals indicating the average current during a switch conduction interval. The time-averaged signals are added up and re-scaled based on the time period of the switching nodes' electrical coupling to the converter output nodes to generate an output signal for the average output current.Type: ApplicationFiled: May 1, 2023Publication date: November 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Stefano RAMORINI, Giuseppe CALDERONI
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Patent number: 11805223Abstract: Current signals indicative of sensed physical quantities are collected from sensing transistors in an array of sensing transistors. The sensing transistors have respective control nodes and current channel paths therethrough between respective first nodes and a second node common to the sensing transistors. A bias voltage level is applied to the respective first nodes of the sensing transistors in the array and one sensing transistor in the array of sensing transistors is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the array of sensing transistors maintain coupling to the bias voltage level. The respective first node of the selected sensing transistor in the array of sensing transistors is coupled to an output node, and an output current signal is collected from the output node.Type: GrantFiled: May 16, 2022Date of Patent: October 31, 2023Assignee: STMicroelectronics S.r.l.Inventors: Pierpaolo Lombardo, Michele Vaiana
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Patent number: 11804814Abstract: A digital audio playback circuit includes a noise shaping circuit configured to receive an input digital audio signal, and a digital to analog converter (DAC) configured to convert the input digital audio signal to a pre-amplified output analog audio signal according to a gain ramp defined by a gain control signal. A muting circuit is configured to compare input digital audio signal to a threshold and assert a mute control signal when the input digital audio signal is below the threshold. An analog gain control ramp circuit is configured to generate the gain control signal in response to the mute control signal to cause the gain ramp to ramp down. An amplifier is configured to amplify the pre-amplified output analog audio signal for playback by an audio playback device.Type: GrantFiled: April 13, 2022Date of Patent: October 31, 2023Assignee: STMicroelectronics S.r.l.Inventors: Francesco Stilgenbauer, Paolo Cacciagrano, Giovanni Gonano
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Patent number: 11803226Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.Type: GrantFiled: May 14, 2020Date of Patent: October 31, 2023Assignee: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta′, Sergio Abenda
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Patent number: 11802042Abstract: A method of operating a MEMS device includes generating a MEMS drive signal, and generating and modifying the MEMS drive signal based upon a control signal to produce a modified drive signal. The method further includes generating the control signal by determining when a feedback signal from the MEMS device is at its peak value, comparing the peak value to a desired value when the feedback signal is as its peak, and generating the control signal depending upon whether the peak value is at least equal to a desired value. The modification of the MEMS drive signal based upon the control signal to produce the modified drive signal includes skipping generation of a next pulse of the modified drive signal when the control signal indicates the peak value is at least equal to the desired value.Type: GrantFiled: December 10, 2020Date of Patent: October 31, 2023Assignee: STMicroelectronics S.r.l.Inventor: Davide Terzi
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Patent number: 11796568Abstract: Cantilever probes are produced for use in a test apparatus of integrated electronic circuits. The probes are configured to contact corresponding terminals of the electronic circuits to be tested during a test operation. The probe bodies are formed of electrically conductive materials. On a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region is formed having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.Type: GrantFiled: October 7, 2021Date of Patent: October 24, 2023Assignee: STMicroelectronics S.r.l.Inventor: Alberto Pagani