Abstract: A method to parameterize and recognize circular gestures on touch sensitive surfaces includes dividing the touch sensitive surface into four quadrants, detecting a transition from a first quadrant into a second quadrant, time-stamping and tracking each detected quadrant transition, and computing the time between quadrant transitions so that the circular speed and direction of the circular gestures on the touch sensitive surface can be detected. The detected direction can be either a clockwise or a counter-clockwise direction.

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

Abstract: A method of sensing the air/fuel ratio in a combustion chamber of an internal combustion engine that may be easily implemented by a respective low-cost device includes a pressure sensor and a learning machine that generates a sensing signal representing the air/fuel ratio by processing the waveform of the pressure in at least one cylinder of the engine. In practice, the learning machine extracts characteristic parameters of the waveform of the pressure and as a function of a certain number of them generates the sensing signal.

Abstract: A voltage regulator includes an amplifier and a regulation loop. The regulator includes a first PMOS transistor connected to a terminal supplying an input voltage, a second PMOS transistor connected in series with the first PMOS transistor. A node between those two transistors defines an output terminal. A first source of a first polarization current of fixed value is connected to the gate of the first transistor, and a second source of a second polarization current of fixed value connects the second transistor to ground. A third NMOS transistor is connected between the two current sources. A circuit is provided to modify automatically at least one of the polarization currents in relation to the load current.

Abstract: Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell.

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract: An antenna generating an electromagnetic field for an electromagnetic transponder and a terminal provided with such an antenna. The antenna comprises a first inductive element designed to be connected to two terminals employing an energizing voltage, and a parallel resonant circuit coupled with the first inductive element.

Abstract: The present disclosure is directed to a thin film resistor having a first resistor layer having a first temperature coefficient of resistance and a second resistor layer on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 50 and 150 angstroms and the second resistor layer may have a thickness in the range of 20 and 50 angstroms.

Abstract: An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.

Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocs of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.

Abstract: An embodiment of an arrangement for detecting sequences of digitally modulated symbols from multiple sources. The arrangement identifies a suitable set of candidate values for at least one transmitted sequence of symbols and determines for each candidate value a set of sequences of transmitted symbols. The arrangement estimates at least one further set of sequence of transmitted symbols, calculates a metric for each sequence of transmitted symbols and selects the sequence that maximizes the metric. At the end, a-posteriori bit soft output information for the selected sequence is calculated from the metrics for said sequences. Generally, these calculations are base on the information coming from a channel state information matrix and a-priori information on said modulated symbols from a second module, such as a forward error correction code decoder.

Abstract: A voltage signal multiplexer includes a control and bias stage to generate at least one control and bias signal as a function of first and second selection signals and first and second input voltage signals. The multiplexer further comprises a switching stage configured to receive the at least one first control and bias signal and to generate therefrom, on an output terminal, an output signal having the first input voltage signal in response to the first and the second selection signals indicating the selection of the first input voltage signal, and having the second input voltage signal in response to the first and the second selection signals indicating the selection of the second input voltage signal. The switching stage is also configured to place the output terminal in a high-impedance condition in response to the first and the second selection signals indicating the high-impedance condition.

Abstract: The electronic device comprises a first terminal and a second terminal, a buffer connected between the first terminal and the second terminal and comprising a signal input, and means for protecting against electrostatic discharges likely to occur across at least a pair of nodes of the buffer. The device comprises at least one integrated structure connected between the two nodes and said signal input, containing at least one MOS transistor and forming both said protection means and at least a part of said buffer.

Abstract: A method for following up a transaction in a network comprising at least one node and at least two data transmission links connected to the node and managed in accordance with at least one data transmission protocol, the method comprising picking up transactions during their transmission by links of the network, converting the transactions picked up into a same format, memorizing converted transactions, so as to be able to identify a link where each memorized transaction has been picked up, and comparing a converted transaction and to be correlated with memorized transactions, the transaction to be correlated being correlated with a memorized transaction if the comparison reveals a correspondence between the transactions to be correlated and memorized.

Abstract: A semiconductor package includes a substrate, a stiffener ring coupled to the substrate and configured to form a well with the substrate, and a die positioned in the well. A thermal interface is positioned on the die. A heat spreader is coupled to the stiffener ring so that a portion of the heat spreader is positioned in the well and the thermal interface thermally couples the heat spreader to the die. The portion of the heat spreader positioned in the well adds rigidity to the semiconductor package and facilitates the use of thin dies.

Abstract: Methods and systems are described for enabling the viewing of positionally and orientationally modified stereoscopic video material using one or more participants with near-to-eye displays with video content appearance altered to accommodate changes in orientation and position of the display.

Abstract: A DC-DC converter based switching voltage regulator circuit is for powering a microprocessor including regulated power supplies configured to produce different output voltages. The DC-DC converter has an output power stage configured to generate a regulated DC supply voltage and comprising a plurality of power transistors. A driver circuit is configured to drive the plurality of power transistors at an adjustable drive voltage in response to a drive control signal. Circuitry is configured to adaptively adjust the adjustable drive voltage and has a voltage selector configured to select between at least two different output voltages for the regulated power supplies of the microprocessor to be coupled to the driver circuit. The voltage selector is controlled by a state logic signal generated based upon logic signals generated by the microprocessor, the state logic signal indicating whether the microprocessor is entering a given power state.

Abstract: The present disclosure is directed to a thin film resistor structure that includes a resistive element electrically connecting first conductor layers of adjacent interconnect structures. The resistive element is covered by a dielectric cap layer that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.

Abstract: A switched-mode converter includes first and second chopper transistors, and control means for maintaining the first and second chopper transistors respectively on and off during first operating phases. The first and second chopper transistors are maintained respectively off and on during second operating phases. An intermediary voltage is applied to the gate of the second transistor during intermediary phases taking place between the first and second phases. This intermediary voltage is close to the threshold voltage of the second transistor.

Abstract: An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.