Patents Assigned to STMicroelectronics AS
  • Patent number: 10503228
    Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Alan Osamu Kobayashi
  • Patent number: 10505580
    Abstract: A digital-to-analog converter (DAC) and a method for operating the DAC are disclosed. The DAC receives, over a first channel, a control signal that is transmitted in accordance with a binary protocol. The DAC also receives, over a second channel different than the first channel, data that is transmitted in accordance with a multilevel communication protocol that is different than the binary protocol. The DAC determines a plurality of first and second voltages based on the received data and identifies, based on the control signal, a time when data transmission or reception is switched between first and second antennas. In response to identifying, based on the control signal, the time when data transmission or reception is switched, the DAC outputs the determined plurality of first voltages to a first antenna tuning circuit or the determined plurality of second voltages to a second antenna tuning circuit.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 10, 2019
    Assignees: STMicroelectronics (Shenzhen) R&D Co. Ltd, STMicroelectronics (Tours) SAS
    Inventors: Songfeng Zhao, Jean Pierre Proot
  • Patent number: 10505043
    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 10504031
    Abstract: An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 10, 2019
    Assignees: STMicroelectronics International N.V., STMicroelectronics, Inc.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Kashif R. J. Meer, Indra Narayan Kar, Rajendar Bahl
  • Patent number: 10504806
    Abstract: One or more embodiments are directed to semiconductor packages that include conductive test pads that are electrically coupled to, but distinct from, the leads of the package. In one embodiment the test pads are located on the plastic packaging material, such as encapsulation material, of the package and are electrically coupled to the leads of the package by traces. The traces may also be located on the packaging material and portions of the leads. In one embodiment, all of the test pads are located on a single surface of the packaging material of the package, which may allow for ease of electrical testing of the package.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10505552
    Abstract: An electronic device disclosed herein includes a locked loop circuit configured to receive a reference signal intended to have an intended frequency, wherein the locked look circuit is intended to generate an intended output signal having an intended frequency equal to the intended frequency multiplied by an intended multiplier. A frequency counter counts a number of pulses of the reference signal during a time window so as to determine an actual frequency of the reference signal. A control circuit determines an actual multiplier for the locked loop circuit that, when multiplied by the actual frequency of the reference signal, causes the locked loop circuit to generate an actual output signal having an actual frequency equal to the intended frequency.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Gupta, Nitin Jain
  • Patent number: 10503326
    Abstract: An electronic device disclosed herein includes a display layer generating display noise based on scanning thereof, and a sensing layer including a plurality of sense lines. A common voltage layer is coupled to the display layer and the sensing layer, with the common voltage layer capacitively coupling the display noise from the display layer to the each of the plurality of sense lines of the sensing layer via a different parasitic impedance. An amplitude of the display noise seen at an input to each sense line is a function of a location of that sense line. The electronic device includes a plurality of compensation impedances, with each compensation impedance coupled to a different one of the plurality of sense lines. Each of the plurality of compensation impedances has an impedance value such that an amplitude of the display noise at an output of each sense line is substantially equal.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Leonard Liviu Dinu, Chee Weng Cheong, Eng Jye Ng
  • Patent number: 10504897
    Abstract: An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 10, 2019
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon
  • Patent number: 10502816
    Abstract: A ranging apparatus includes an array of light sensitive detectors configured to receive light from a light source which has been reflected by an object. The array includes a number of different zones. Readout circuitry including at least one read out channel is configured to read data output from each of the zones. A processor operates to process the data output to determine position information associated with the object.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 10, 2019
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Bruce Rae, Pascal Mellot, John Kevin Moore, Graeme Storm
  • Patent number: 10503259
    Abstract: A vibrating device comprises: a first support configured to be deformed having a surface defined in a plane in directions X and Y; at least one actuator configured to generate plate modes propagated in the first support; the first support comprising: at least one defect with respect to the propagation of the plate modes; the defect being of geometrical nature or corresponding to a structural heterogeneity; comprising: a second support; at least one embedded mechanical reflector secured to the first support and in contact with the first support, configured to immobilize the first support in at least one direction Z at right angles to the directions X and Y, the mechanical reflector being secured to the second support and; the embedded mechanical reflector being configured to isolate a so-called active zone belonging to the surface defined in a plane in directions X and Y in which the plate modes are propagated, the active zone excluding the defect; the actuator being situated in the active region.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 10, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS, UNIVERSITE GRENBOLE ALPES, INSTITUT POLYTECHNIQUE DE GRENOBLE
    Inventors: Cédrick Chappaz, Fabrice Casset, Skandar Basrour, Marie Gorisse
  • Patent number: 10505562
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 10502777
    Abstract: A method of testing a first circuit, including: a) applying a first signal between two terminals of the first circuit, the first circuit being powered off; and b) verifying that radio frequency waves transmitted by the first circuit correspond to an expected transmission.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Yann Bacher, Nicolas Froidevaux
  • Patent number: 10502784
    Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Satinder Singh Malhi
  • Patent number: 10505254
    Abstract: A near field communications (NFC) transponder includes a transmit circuit coupled to a transmit antenna and a receive circuit coupled to a receive antenna. The transmit/receive antennae are configured such that no signal is induced on the receive antenna by operation of the transmit antenna. Advantageously, this permits continued reception by the receive antenna while the transmit antenna is used for transmission using active load modulation.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Mohammad Mazooji
  • Patent number: 10503663
    Abstract: A method for secure processing of encrypted data within a receiver includes receiving a packet of encrypted compressed data and allocating a region of memory for storing a decrypted version of the packet of encrypted compressed data. The allocation is in response to, and after, reception of the encrypted compressed data. A size of the region of the memory allocated is equal to a size of the packet of encrypted compressed data that is received. The method further includes modifying a configuration of an access authorization filter for defining access rights to the allocated region, decrypting the packet of encrypted compressed data, and storing, in the allocated region, the decrypted compressed data of the packet. The aforementioned allocation, modification, decryption, and storage steps are repeated in response to each new reception of a packet of encrypted compressed data so as to dynamically modify the configuration of the access authorization filter.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Jean-Philippe Fassino, Roland Bohrer, Laurent Gerard
  • Patent number: 10506680
    Abstract: A driving apparatus configured to drive a light emitting device includes a driving current source module operable to supply current to the light emitting device via a node during operation. A protection module coupled to the node and the driving current source module selectively injects current to the node during operation. The driving current source module is controlled based on a detection result of a voltage on the node.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventors: Tao Tao Huang, Yi Jun Duan
  • Publication number: 20190372535
    Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Stefano RAMORINI, Alberto CATTANI, Germano NICOLLINI, Alessandro GASPARINI
  • Publication number: 20190371858
    Abstract: A MOS transistor with two vertical gates is formed within a substrate zone of a semiconductor substrate doped with a first type of conductivity and separated from a remaining portion of the substrate by two first parallel trenches extending in a first direction. An isolated gate region rests on each flank of the substrate zone and on a portion of the bottom of the corresponding trench to form the two vertical gates. At least one gate connection region electrically connects the two vertical gates. A first buried region located under the substrate zone is doped with a second type of conductivity to form a first conduction electrode of the MOS transistor. A second region doped with the second type of conductivity is located at the surface of the substrate zone to form a second conduction electrode of the MOS transistor.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Philippe BOIVIN, Jean-Jacques FAGOT
  • Publication number: 20190372537
    Abstract: An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Vincent BINET, Yohan JOLY
  • Publication number: 20190372393
    Abstract: A contactless card is powered by an antenna connected to the input of a rectifier. An output of the rectifier is coupled to a processing unit that consumes a first current output from the rectifier. A current regulation circuit is connected to the output of the rectifier. The current regulation circuit operates to absorb a second current from the output of the rectifier such that a sum of the first and second currents is a constant current.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics SA
    Inventor: Julien GOULIER