Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.

Abstract: A method begins with forming a first wiring layer on a substrate, forming a cavity in the substrate, and laminating a bottom side of the substrate so as to cover a bottom side of the cavity. Next, an integrated circuit is placed within the cavity of the substrate, and then a first optically transparent layer is disposed on the top surface of the substrate to cover a top surface of the integrated circuit. The first optically transparent layer has an aperture formed therein exposing at least a portion of the top surface of the integrated circuit. A second wiring layer is disposed on a top surface of the first optically transparent layer in a pattern that does not obstruct light traveling to or from the top surface of the integrated circuit. The integrated circuit is a laser emitting integrated circuit or a reflected light detector.

Abstract: A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.

Abstract: A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

Abstract: Disclosed herein is a MEMS device including a fixed structure, a mobile structure, and deformable structures extending therebetween. The deformable structures have first ends anchored along X and Y axes of the fixed structure, and have second ends anchored offset from the X and Y axes of the fixed structure. The deformable structures are shaped so as to curve from their anchoring points along the mobile structure back toward the mobile structure, to extend along the perimeter of the mobile structure, and to then curve away from the mobile structure and toward their anchoring points along the fixed structure. Each deformable structure has two piezoelectric elements that extend along the length of that deformable structure, with one piezoelectric element having a greater length than the other piezoelectric element.

Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debugging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

Abstract: The invention relates to an image sensor and method for reducing image defects. A photoconversion area is formed in a semiconductor layer. An insulating layer formed over the semiconductor layer contains a metal element. A lens over the insulting layer is positioned opposite the photoconversion area to focus light on it. A layer of light-absorbing material is deposited on the side of the metal element facing the lens to prevent reflection of parasitic light rays within the image device.

Abstract: Ejection device for fluid, comprising a solid body including: first semiconductor body including a chamber for containing the fluid, an ejection nozzle in fluid connection with the chamber, and an actuator operatively connected to the chamber to generate, in use, one or more pressure waves in the fluid such as to cause ejection of the fluid from the ejection nozzle; and a second semiconductor body including a channel for feeding the fluid to the chamber, coupled to the first semiconductor body, in such a way that the channel is in fluid connection with the chamber. The second semiconductor body integrates a damping cavity over which extends a damping membrane, the damping cavity and the damping membrane extending laterally to the channel for feeding the fluid.

Abstract: A control system for an ultrasound transmission/reception apparatus with a plurality of acoustic transducers for transmitting and receiving ultrasound signals may include driving device operatively coupled to the acoustic transducers and a control unit. The control unit may cyclically control the acoustic transducers in a transmission state for transmitting ultrasound signals, and in a reception state for receiving echoes of the transmitted ultrasound signals. The control unit may include an input stage which receives an external timing signal, and a processing stage which detects a first edge of the timing signal to determine the start time of a transmission phase during which the acoustic transducers are controlled in the transmission state, and a second edge of the timing signal to determine the stop time of a reception phase during which the acoustic transducers are controlled in the reception state.

Abstract: In an embodiment, a method is provided for controlling a level of a read current in a non-volatile memory that is powered by a supply voltage includes. A model current representative of an actual current able to flow during a readout through a read path of the memory is determined based on the value of the supply voltage. The model current is compared to a reference current having a reference value. A control signal is generated. The control signal is to control the generation of the read current having a level equal to the lowest value between a fraction of the value of the model current and the reference value.

Abstract: In an embodiment, a device may include a first sensor configured to generate first sensor data during a first time period and a second time period; a second sensor configured to be disabled during the first time period, the second sensor further being configured to generate second sensor data during the second time period; and a processor configured to determine a characteristic of the first sensor data during the first time period. The device may further include a classifying circuit configured to determine, during the first time period, whether the device has changed state based on the characteristic of the first sensor data, the classifying circuit further being configured to cause the second sensor to be enabled in response to a change in a state of the device.

Abstract: An auto-tuned ramp generator and a method for generating a sawtooth signal are provided. In the method and apparatus, a sawtooth signal is compared to a first reference voltage and a second reference voltage. In response to determining that the sawtooth signal does not exceed the first reference voltage, the voltage level of the sawtooth signal is increased. In response to determining that the sawtooth signal exceeds the second reference voltage, the voltage level of the sawtooth signal is decreased. The voltage level the sawtooth signal is retained if the sawtooth signal remains between the first and second reference voltages.

Abstract: A packaged semiconductor device includes an insulating material forming a side surface of the packaged semiconductor device. An integrated-circuit chip is embedded in the insulating material and includes a communication circuit. A wiring system is embedded in the insulating material and electrically couples the integrated-circuit chip with a plurality of package contact elements. A first communication pad is formed in the side surface and is operatively coupled to the communication circuit to enable signal exchange through the first communication pad.

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract: In one embodiment, an imaging device includes a light-emitting device, a driving circuit, a return single-photon avalanche diode (SPAD) array and readout circuitry. The driving circuit generates a driving signal, and the light-emitting device generates an optical pulse based on the driving signal. The return SPAD array is configured to receive a first portion of the optical pulse that is reflected by an object in an image scene. The readout circuitry receives a signal indicative of the received first portion of the optical pulse, and a signal indicative of the driving signal, and determines a distance between the imaging device and the object based on a difference between a time of receiving the signal indicative of the received first portion of the optical pulse and a time of receiving the signal indicative of the driving signal.

Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.

Abstract: An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.

Abstract: A capacitive sensing structure includes a first sensing electrode located in a first layer for sensing a first capacitance and producing a first sense signal indicative of the sensed first capacitance. A transmit electrode is located in the first layer and positioned surrounding 90%+ of a perimeter of the first sensing electrode. A second sensing electrode is located in the first layer and positioned surrounding 90%+ of a perimeter of the transmit electrode, the second sensing electrode to sense a second capacitance and produce a second sense signal indicative of the sensed second capacitance. Controller circuitry receives the first and second sense signals, compares a change in the sensed first capacitance to a change in the sensed second capacitance, and produces an output signal indicative of a user touch based upon the comparison between the change in the sensed first capacitance and the change in the sensed second capacitance.

Abstract: Digital image processing circuitry clusters a set of images into a set of first clusters of images and a set of unclustered images. The set of first clusters are merged, generating a set of second clusters of images. Images in the set of unclustered images are assigned to one of a cluster of the set of second clusters of images and an outlier image cluster. The clustered images may be partitioned into subclusters based on detection of objects in the images.