Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
Type:
Grant
Filed:
September 8, 2017
Date of Patent:
November 26, 2019
Assignees:
STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
Abstract: A time-of-flight detection pixel includes a photosensitive area including a first doped layer and a charge collection area extending in the first doped layer. At least two charge storage areas extend from the charge collection area, each including a first well more heavily doped than the charge collection area and separated from the charge collection area by a first portion of the first doped layer which is coated with a gate. Each charge storage area is laterally delimited by two insulated conductive electrodes, extending parallel to each other and facing each other. A second heavily doped layer of opposite conductivity coats the pixel except for at each portion of the first doped layer coated with the gate.
Type:
Grant
Filed:
December 22, 2016
Date of Patent:
November 26, 2019
Assignees:
STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventors:
Francois Roy, Marie Guillon, Yvon Cazaux, Boris Rodrigues, Alexis Rochas
Abstract: A MEMS device including a main die that may be coupled to a secondary die, which forms a frame, and at least one first mobile mass elastically coupled to the frame, the main die forming: a driving stage that drives the first mobile mass so that it oscillates, parallel to a first direction, with frequency-modulated displacements; and a processing stage, which generates an output signal indicating an angular velocity of the MEMS device as a function of displacements parallel to a second direction that are made by the first mobile mass, when driven by the driving stage, on account of a Coriolis force.
Type:
Grant
Filed:
March 22, 2017
Date of Patent:
November 26, 2019
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Gabriele Gattere, Alessandro Tocchio, Carlo Valzasina
Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
Type:
Grant
Filed:
January 7, 2019
Date of Patent:
November 26, 2019
Assignee:
STMicroelectronics (Rousset) SAS
Inventors:
Guilhem Bouton, Pascal Fornara, Christian Rivero
Abstract: Method for generating a lane departure warning in a vehicle, comprising acquiring a plurality of frames of a digital image of a road on which the vehicle is running, the digital image of a road including the image of a lane within which the vehicle is running and of marking lines of the lane, for each of the acquired frames, extracting edge points of the frame, analyzing the edge points to evaluate a lane departure status, the evaluation including performing a lane departure verification procedure including identifying in the frame points representative of the position of the lane marking lines, generating a lane departure alert if a lane departure status is detected by the lane departure verification procedure.
Type:
Grant
Filed:
June 30, 2017
Date of Patent:
November 26, 2019
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Nunziata Ivana Guarneri, Arcangelo Ranieri Bruna
Abstract: A voltage comparator for detecting a voltage difference in a high-voltage domain, wherein said comparator receives an input voltage and compares it with a reference voltage also received in input, in which the output voltage from the comparator assumes the logic value 1 if the input voltage is greater than the reference voltage and assumes the logic value 0 if the input voltage is less than or equal to the reference voltage, wherein said comparator comprises low-voltage components and a single high-voltage component. In particular, the low-voltage components are MOS transistors and the high-voltage component is a high-voltage PMOS.
Type:
Grant
Filed:
March 13, 2017
Date of Patent:
November 26, 2019
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Alberto Iorio, Jeanpierre Vicquery, Emilio Volpi
Abstract: An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the semiconductor body; and a conductive wire, electrically connected to the front metallization region. The top buffer region is at least partially sintered.
Abstract: A method of manufacturing an optical device is disclosed. The method includes forming a waveguide in a glass plate. The method further includes scanning the glass plate with a laser beam directed at an acute angle with respect to a first surface to form a mirror trench in the glass plate. Scanning the glass plate with the first laser beam includes pulses of the laser beam that have a duration between 2 and 500 femtoseconds. The method also includes filling the mirror trench with a reflective material and depositing a cladding layer over the waveguide and mirror trench.
Type:
Grant
Filed:
August 10, 2018
Date of Patent:
November 26, 2019
Assignee:
STMICROELECTRONICS SA
Inventors:
Cédric Durand, Frédéric Gianesello, Folly Eli Ayi-Yovo
Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.
Abstract: The half-bridges driving a multiphase motor are controlled to perform a sequence of operations to support charging a hold capacitor. First, in a brake configuration, the half-bridge transistors are controlled such that either high-side transistors or low-side transistors of the half-bridges are turned on. Second, in an active step-up configuration, the half-bridge transistors are controlled such that the high-side transistor of a first half-bridge and the low-side transistor of a second half-bridge are both turned on and the low-side transistor of the first half-bridge and the high-side transistor of the second half-bridge are both turned off. Third, in an active brake configuration, the half-bridge transistors are controlled such that the low-side transistor of the first half-bridge and the high-side transistor of the second half-bridge are both turned on and the high-side transistor of the first half-bridge and the low-side transistor of the second half-bridge stage are both turned off.
Type:
Application
Filed:
May 13, 2019
Publication date:
November 21, 2019
Applicant:
STMicroelectronics Asia Pacific Pte Ltd
Abstract: The supply voltage for a module of an integrated circuit managed to support protection against side channel attacks. Upon startup of the integrated circuit, one action from the following actions is selected in response to a command: supplying the module with the supply voltage having a fixed value that is selected from a plurality of predetermined values, or varying the value of the supply voltage in time with a pulsed signal.
Type:
Application
Filed:
May 14, 2019
Publication date:
November 21, 2019
Applicant:
STMicroelectronics (Rousset) SAS
Inventors:
Alexandre SARAFIANOS, Thomas ORDAS, Yanis LINGE, Jimmy FORT
Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
Type:
Application
Filed:
May 14, 2019
Publication date:
November 21, 2019
Applicants:
STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
Abstract: Testing of control wires of a pixel array of an image sensor is performed by applying a signal transition to a control wire and detecting, based on a voltage signal detected on the control wire, the duration of at least part of the signal transition on the control wire. An electrical fault in the control wire is indicated based on a comparison of the detected duration to a threshold.
Type:
Grant
Filed:
October 20, 2015
Date of Patent:
November 19, 2019
Assignee:
STMicroelectronics (Grenoble 2) SA
Inventors:
Richun Fei, Salvador Mir, Jocelyn Moreau
Abstract: A multi-axis MEMS gyroscope includes a micromechanical detection structure having a substrate, a driving-mass arrangement, a driven-mass arrangement with a central window, and a sensing-mass arrangement which undergoes sensing movements in the presence of angular velocities about a first horizontal axis and a second horizontal axis. A sensing-electrode arrangement is fixed with respect to the substrate and is set underneath the sensing-mass arrangement. An anchorage assembly is set within the central window for constraining the driven-mass arrangement to the substrate at anchorage elements. The anchorage assembly includes a rigid structure suspended above the substrate that is elastically coupled to the driven mass by elastic connection elements at a central portion, and is coupled to the anchorage elements by elastic decoupling elements at end portions thereof.
Type:
Grant
Filed:
September 22, 2016
Date of Patent:
November 19, 2019
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Gabriele Gattere, Carlo Valzasina, Luca Giuseppe Falorni
Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.
Type:
Grant
Filed:
May 11, 2018
Date of Patent:
November 19, 2019
Assignee:
STMICROELECTRONICS (ROUSSET) SAS
Inventors:
Philippe Boivin, Simon Jeannot, Olivier Weber
Abstract: A heat-transferring device is formed by a stack that includes at least one heat-conducting layer and at least one heat-absorbing layer. The at least one heat-conducting layer has at least one heat-collecting section placed facing a heat source and at least one heat-evacuating section placed facing a heat sink. The at least one heat-absorbing layer includes a phase-change material. One face of the at least one heat-absorbing layer is adjoined to at least one portion of at least one face of the heat-conducting layer.
Type:
Grant
Filed:
November 2, 2017
Date of Patent:
November 19, 2019
Assignees:
STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
Inventors:
Rafael Augusto Prieto Herrera, Jean-Philippe Colonna, Perceval Coudrain
Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
Abstract: An integrated circuit chip is mounted to a front face of a support plate. An encapsulation cap in then mounted to the support plate. The encapsulation cap includes a front wall and a peripheral wall having an end edge at least partly facing a peripheral zone of the support plate. The support plate and the encapsulation cap delimit a chamber in which the integrated circuit chip is situated. To mount the encapsulation cap, a bead of glue is inserted between the peripheral zone and the end edge of the peripheral wall of the encapsulation cap. A peripheral outer face of the encapsulation cap includes a recess extending from the end edge which locally uncovers a part of the bead of glue. A local hardening of the glue at the recess is performed as a first attachment step. Further hardening of the remainder of the glue is then performed.
Abstract: A reversible converter includes a first field effect transistor and a second field effect transistor coupled in series between a first terminal and a second terminal for a DC voltage. A first thyristor and a second thyristor are coupled in series between the first and second terminals for the DC voltage. A third thyristor and a fourth thyristor are also coupled in series between the first and second terminals for the DC voltage terminals, but have an opposite connection polarity with respect to the first and second thyristors. A midpoint of connection between the first and second field effect transistors and a common midpoint of connection between the first and second thyristors and the third and fourth thyristors are coupled to AC voltage terminals. Actuation of the transistors and thyristors is controlled in distinct manners to operate the converter in an AC-DC conversion mode and a DC-AC conversion mode.
Type:
Grant
Filed:
June 27, 2018
Date of Patent:
November 19, 2019
Assignee:
STMicroelectronics (Tours) SAS
Inventors:
Ghafour Benabdelaziz, Cedric Reymond, David Jouve
Abstract: Provided is an acoustic transducer including: a semiconductor substrate; a vibrating membrane, provided above the semiconductor substrate, including a vibrating electrode; and a fixed membrane, provided above the semiconductor substrate, including a fixed electrode, the acoustic transducer detecting a sound wave according to changes in capacitances between the vibrating electrode and the fixed electrode, converting the sound wave into electrical signals, and outputting the electrical signals. At least one of the vibrating electrode and the fixed electrode is divided into a plurality of divided electrodes, and the plurality of divided electrodes outputting the electrical signals.