Patents Assigned to STMicroelectronics AS
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Publication number: 20240151741Abstract: The MEMS device is formed by a substrate and a movable structure suspended on the substrate. The movable structure has a first mass, a second mass and a first elastic group mechanically coupled between the first and the second masses. The first elastic group is compliant along a first direction. The first mass is configured to move with respect to the substrate along the first direction. The MEMS device also has a second elastic group mechanically coupled between the substrate and the movable structure and compliant along the first direction; and an anchoring control structure fixed to the substrate, capacitively coupled to the second mass and configured to exert an electrostatic force on the second mass along the first direction.Type: ApplicationFiled: October 27, 2023Publication date: May 9, 2024Applicant: STMICROELECTRONICS S.r.l.Inventors: Manuel RIANI, Gabriele GATTERE, Francesco RIZZINI
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Patent number: 11977190Abstract: A device such as a dosimeter for detecting ionizing radiation, for example, X-ray radiation, in hospitals or the like. The device includes scintillator material configured to produce light as a result of radiation interacting with the scintillator material, and photoelectric conversion circuitry optically coupled to the scintillator material and configured to produce electrical signals via photoelectric conversion of light produced by the scintillator material. The device includes a plurality of photoelectric converters optically coupled with the scintillator material at spatially separated locations. The plurality of photoelectric converters thus produce respective electrical signals by photoelectric conversion of light produced by the scintillator material as a result of radiation interacting with the scintillator material. Improved energy linearity is thus facilitated while providing more efficient detection over the whole energy spectrum of radiation detected.Type: GrantFiled: June 30, 2020Date of Patent: May 7, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Sara Loi, Paolo Crema, Alessandro Freguglia
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Patent number: 11979167Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.Type: GrantFiled: July 28, 2022Date of Patent: May 7, 2024Assignee: STMicroelectronics International N.V.Inventors: Sharad Gupta, Ankur Bal
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Patent number: 11979143Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.Type: GrantFiled: July 21, 2022Date of Patent: May 7, 2024Assignee: STMicroelectronics S.r.l.Inventors: Nicola Errico, Valerio Bendotti, Luca Finazzi, Gaudenzia Bagnati
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Patent number: 11977971Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.Type: GrantFiled: February 10, 2023Date of Patent: May 7, 2024Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.r.lInventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
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Patent number: 11979153Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.Type: GrantFiled: April 29, 2022Date of Patent: May 7, 2024Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Jean-Francois Link, Mark Wallis, Joran Pantel
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Patent number: 11978756Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 21, 2020Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
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Patent number: 11978710Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.Type: GrantFiled: June 28, 2021Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Didier Dutartre
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Patent number: 11978530Abstract: A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.Type: GrantFiled: December 20, 2021Date of Patent: May 7, 2024Assignee: STMicroelectronics SAInventor: Faress Tissafi Drissi
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Patent number: 11977424Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down.Type: GrantFiled: March 23, 2022Date of Patent: May 7, 2024Assignees: STMicroelectronics Application GmbH, STMicroelectronics S.r.l.Inventors: Roberto Colombo, Nicolas Bernard Grossier
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Patent number: 11977438Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.Type: GrantFiled: August 19, 2021Date of Patent: May 7, 2024Assignee: STMicroelectronics Application GMBHInventor: Roberto Colombo
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Patent number: 11977186Abstract: In an embodiment, a method includes: resetting respective count values of a plurality of analog counters to an initial count value, each analog counter of the plurality of analog counters corresponding to a histogram bin of a time-of-flight (ToF) histogram; after resetting the respective count values, receiving a plurality of digital addresses from a time-to-digital converter (TDC); during an integration period, for each received digital address, selecting one analog counter based on the received digital address, and changing the respective count value of the selected one analog counter towards a second count value by a discrete amount, where each analog counter has a final count value at an end of the integration period; and after the integration period, determining an associated final bin count of each histogram bin of the ToF histogram based on the final count value of the corresponding analog counter.Type: GrantFiled: June 7, 2021Date of Patent: May 7, 2024Assignee: STMicroelectronics (Research & Development) LimitedInventors: Kasper Buckbee, Neale Dutton
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Patent number: 11978411Abstract: A non-emissive display includes a backlight controller sending a pulse during each sub-frame of a plurality of frames to row and column drivers that drive backlight zones. The row drivers count each pulse to keep a pulse count total, and reset the pulse count total when it is equal to a first number indicating how many row drivers are present. Each row driver activates its channels and waits for a next pulse if the pulse count total is not equal to the first number and if the pulse count total is equal to a second number indicating in which sub-frame that first driver is to be activated. Each row driver waits for a next pulse if the pulse count total is not equal to the first number and the second number. Each column driver activates its channel in response to receipt of each pulse.Type: GrantFiled: March 10, 2023Date of Patent: May 7, 2024Assignee: STMicroelectronics S.r.l.Inventors: Gaetano L'Episcopo, Giovanni Conti, Carmelo Occhipinti, Mario Antonio Aleo
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Patent number: 11978416Abstract: Display elements, each having anode and cathode terminals, are arranged into rows and columns. Each row has an anode-line coupled to the anode terminals for its display elements. Each column has a cathode-line coupled to the cathode terminals for its display elements. A switch for each anode-line selectively couples that anode-line to a storage capacitor, and a switch for each cathode-line selectively couples that cathode-line to the storage capacitor. A display driver activates the row driver for a given row and the column driver for a given column. A switch driver closes the switch for the cathode-line for the given column, then opens the switch for that cathode-line. The display driver deactivates the row driver for the given row, after closing the switch for the cathode-line for the given column. The switch driver closes the switch for the anode-line for the given row.Type: GrantFiled: November 21, 2022Date of Patent: May 7, 2024Assignee: STMicroelectronics S.r.l.Inventors: Gaetano L'Episcopo, Giovanni Conti
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Patent number: 11979704Abstract: The present disclosure is directed to a device that includes a headphone speaker housing that includes a coil having a first terminal and a second terminal that is configured to operate in a sound generation mode and a battery charging mode. A class D amplifier circuit is configured to rectify in a battery charging mode and amplify in a sound generation mode, the class D amplifier is coupled to the first terminal and the second terminal of the coil. The class D amplifier including a first, second, third, and fourth switch, the first terminal coupled between the first and second switch, the second terminal coupled between the third and fourth switch. An audio generation circuit having a third terminal and a fourth terminal, the third terminal coupled between the first and third switch of the class D amplifier and the fourth terminal coupled between the second and fourth switch of the class D amplifier. A battery charging circuit coupled to the third terminal and the fourth terminal.Type: GrantFiled: November 29, 2021Date of Patent: May 7, 2024Assignee: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.Inventors: Tomas Teply, Karel Blaha
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Publication number: 20240146324Abstract: Offset calibration for an analog front-end system is provided. The analog front-end system includes a variable-gain amplifier, and the calibration mitigates an offset error of the variable-gain amplifier. Calibration is based on a difference-based estimation technique combined with digital iteration. Difference-based estimation includes measuring different digital output signals from an analog-to-digital converter for different respective gains of the variable-gain amplifier. The digital iteration is utilized to estimate offsets values which converge a digital output difference to a target of zero volts.Type: ApplicationFiled: October 6, 2023Publication date: May 2, 2024Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Anubhuti CHOPRA
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Publication number: 20240145500Abstract: An array of single photon avalanche diodes (SPADs) includes a plurality of pixels. Each pixel includes a SPAD having a cathode connected to a first intermediate node and an anode coupled to first negative voltage, a quench circuit connected between the first intermediate node and the low voltage supply node, an AC coupling element connected between the first intermediate node and a second intermediate node, a filter component connected between the high voltage node and the second intermediate node, and an inverter having its input connected to the second intermediate node and its output providing an output signal. A resistance associated with the quench circuit, a capacitance associated with the SPAD, a capacitance associated with the AC coupling element, and a resistance associated with the filter component form a variable second order filter.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Applicant: STMicroelectronics (Research & Development) LimitedInventors: Mohammed AL-RAWHANI, Bruce RAE
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Publication number: 20240141543Abstract: Articles such as substrates for semiconductor products comprising metal and resin portions with adhesion promoter material are processed in a plating bath, wherein the adhesion promoter material is exposed to dissolution as a result of prolonged exposure to the plating bath. The articles are processed by dipping them in the processing bath so that they have opposed surfaces exposed to the processing bath. The movement of the articles through the processing bath B may occur to be halted. In that case a gas flow is provided lapping the opposed surfaces of the articles to shield the opposed surfaces of the articles from exposure to the processing bath.Type: ApplicationFiled: October 27, 2023Publication date: May 2, 2024Applicant: STMICROELECTRONICS S.r.l.Inventor: Paolo CREMA
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Publication number: 20240142806Abstract: A device includes a first pixel, based on quantum dots, configured to deliver event-based data for generating an event-based image, and second pixels, each second pixel based on quantum dots, configured to deliver light intensity data for generating a light intensity image.Type: ApplicationFiled: October 24, 2023Publication date: May 2, 2024Applicant: STMicroelectronics (Crolles 2) SASInventor: Arthur ARNAUD
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Publication number: 20240145258Abstract: The present disclosure is directed to at least one semiconductor package including a die within an encapsulant having a first sidewall, an adhesive layer on the encapsulant and having a second sidewall coplanar with the first sidewall of the encapsulant, and an insulating layer on the adhesive layer having a third sidewall coplanar with the first sidewall and the second sidewall. A method of manufacturing the at least one semiconductor package includes forming an insulating layer on a temporary adhesion layer of a carrier, forming an adhesive layer on the insulating layer, and forming a plurality of openings through the adhesive layer and the insulating layer. The plurality of openings through the adhesive layer and the insulating layer may be formed by exposing the adhesive layer and the insulating layer to a laser.Type: ApplicationFiled: October 18, 2023Publication date: May 2, 2024Applicant: STMICROELECTRONICS PTE LTDInventor: David GANI