Abstract: A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.

Abstract: A BGA package includes an array of electrically conductive balls providing electrical contact for a semiconductor die. A power channel is provided to convey power supply current towards the semiconductor die. The power channel is formed by a stack of electrically conductive planes. The electrically conductive planes are stacked in a stepped arrangement wherein a number of stacked planes in each step of the stack increases in a direction from a distal end to a proximal end of the power channel. Adjacent electrically conductive planes in the stack of the power channel are electrically coupled with electrically conductive vias extending therebetween. Current conduction paths towards the die area thus have resistance values that decrease from the distal end to the proximal end of the power channel.

Abstract: A semiconductor die is arranged on a first surface of a leadframe having a first thickness between the first surface and a second surface opposite the first surface and an array of electrically conductive leads. Terminal recesses are provided in the electrically conductive leads in the array at the first surface. At the terminal recesses, the electrically conductive leads have a second thickness less than the first thickness. The semiconductor die is coupled with the electrically conductive leads via wires or ribbons having ends coupled to the electrically conductive leads arranged in the terminal recesses. The leadframe is partially cut starting from the second surface at the terminal recesses with a cutting depth between the first thickness and the second thickness. The partial cut produces exposed surfaces of the electrically conductive leads and the ends of the electrically conductive elongated formations providing wettable flanks for solder material.

Abstract: A leadframe includes a die pad and electrically conductive leads arranged peripherally of the die pad. A semiconductor die is mounted to the die pad. The die is electrically coupled to the electrically conductive leads using an electrical coupling member applied onto the semiconductor die. The electrical coupling member includes a planar body configured to cover the semiconductor die and the electrically conductive leads. The planar body of the electrical coupling member includes strip-like, electrically conductive formations embedded in an electrically insulating material. Each strip-like, electrically conductive formation has a first end configured to contact the semiconductor die and a second end configured to contact the electrically conductive lead.

Abstract: Laser direct structuring, LDS material is molded onto semiconductor dice arranged on die pads in a leadframe and the semiconductor dice are electrically coupled with electrically conductive leads in the leadframe via electrical connections that comprise electrically conductive formations exposed at the front surface of the LDS material, electrically conductive vias between the semiconductor dice and the front surface of the LDS material, as well as electrically conductive lines over the front surface of the LDS material that couple selected ones of the electrically conductive formations with selected ones of the second electrically conductive vias. The electrically conductive vias and lines are provided applying laser beam energy to the front surface of the laser direct structuring material at spatial positions located as a function of the electrically conductive formations exposed at the front surface of the LDS material acting as fiducials.

Abstract: Disclosed herein is a single photon avalanche diode (SPAD) pixel for use in time-of-flight imaging. This pixel includes a SPAD having a cathode connected to a first node and an anode coupled to first negative voltage. A transistor circuit in the pixel includes a quench transistor connected between a supply voltage node and a second node, the quench transistor controlled by a quench control signal to operate in a high-impedance mode, and a recharge transistor connected in parallel with the quench transistor between the supply voltage node and the second node, the recharge transistor controlled by a feedback signal. The pixel also includes a readout inverter generating an output signal based upon a voltage at the first node and an adjustable delay circuit generating the feedback signal based upon the output signal, the feedback signal being delayed with respect to the output signal.

Abstract: The present disclosure is directed to a method for detecting a liquid on a main surface of a body. The method is performed through a detection device including a processing module, a reference electrode at a reference electric voltage and a first sensing electrode on the main surface and configurated to detect an environmental electric and/or electrostatic charge variation indicative of the presence of the liquid. The method includes the steps of: biasing the first sensing electrode to a bias electric voltage; while the first sensing electrode is at the bias electric voltage, acquiring a first charge variation signal indicative of the electric and/or electrostatic charge variation detected by the first sensing electrode; verifying whether the first charge variation signal is indicative of the presence of the liquid on the main surface, at the first sensing electrode; and, if it is, determining the presence of the liquid on the main surface at the first sensing electrode.

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

Abstract: A circuit for use, e.g., as current sense amplifier in a DC-DC converter in a hybrid vehicle includes a first input node and a second input node, configured to have an input voltage signal applied therebetween, a floating-ground input stage configured to operate between a first supply voltage and a second non-zero supply voltage and to convert into a current signal the input voltage signal applied between the first input node and the second input node. The circuit includes an output stage configured to receive the current signal from the floating-ground input stage and to convert the current signal back to an output voltage signal referred to ground. The output voltage referred to ground is a replica of the input voltage signal applied between the first input node and the second input node.

Abstract: Disclosed herein is a DC-DC converter including a power section and a bootstrap circuit for driving the gate of the high-side transistor of the power section. The bootstrap circuit includes an adaptive clamp circuit that maintains a proper voltage differential across the bootstrap capacitor within the bootstrap circuit for recharge during off-times regardless of whether the mode of operation of the DC-DC converter continuous conduction mode (CCM), discontinuous conduction mode (DCM), or pulse-skip mode. This voltage differential is established as being between a bootstrap voltage and a voltage at a tap between the high and low side transistors of the power section. The adaptive clamp circuit maintains the bootstrap voltage as following the lesser of the output voltage and the voltage at the tap.

Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.

Abstract: A device and method for manufacturing a device comprising two semiconductor dice. The device is formed by a first die and a second die. The first die is of semiconductor material and integrates electronic components. The second die has a main surface, forms patterned structures, and is bonded to the first die. Internal electrical coupling structures electrically couple the main surface of the first die to the second die. External connection regions extend on the main surface of the first die. A package packages the first die, the second die and the internal electrical coupling structures and partially surrounds the external connection regions, the external connection regions partially protruding from the package.

Abstract: A microelectromechanical gyroscope with detection along a vertical axis is provided with a detection structure having a movable structure, suspended above a substrate so as to perform, as a function of an angular velocity around the vertical axis a sense movement along a first horizontal axis. The movable structure has at least one drive mass internally defining a window, elastically coupled to a rotor anchor, at an anchoring region, through elastic anchoring elements; at least one bridge element, rigid and of a conductive material, cantilevered suspended and extending within the window along the first horizontal axis, elastically coupled to the drive mass; movable electrodes, carried integrally by the bridge element with extension along a second horizontal axis.

Abstract: A method includes counting a first set of photons having times of flight that falls within a first time range and being detected during a first time period, determining a second time range based on the first set of photons, the second time range being smaller than the first time range, counting a second set of photons having times of flight that fall within the second time range and being detected during a second time period, and determining a third time range based on the second set of photons, the third time range being smaller than the second time range.

Abstract: An embodiment driver circuit comprises a power supply pin configured to receive a power supply voltage, and a set of control pins configured to provide a set of control signals for controlling switching of a set of switches of an h-bridge circuit comprising a pair of high-side switches and a pair of low-side switches. The driver circuit comprises control circuitry coupled to the control pins and configured to generate the control signals, and sensing circuitry coupled to the power supply pin and configured to generate a detection signal indicative of the power supply voltage exceeding a threshold value. The control circuitry is sensitive to the detection signal and is configured to generate the control signals to activate one of the pair of high-side switches and the pair of low-side switches and de-activate the other of the pair of high-side switches and the pair of low-side switches.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Abstract: Embodiments of a Coriolis-force-based flow sensing device and embodiments of methods for manufacturing embodiments of the Coriolis-force-based flow sensing device, comprising the steps of: forming a driving electrode; forming, on the driving electrode, a first sacrificial region; forming, on the first sacrificial region, a first structural portion with a second sacrificial region buried therein; forming openings for selectively etching the second sacrificial region; forming, within the openings, a porous layer having pores; removing the second sacrificial region through the pores of the porous layer, forming a buried channel; growing, on the porous layer and not within the buried channel, a second structural portion that forms, with the first structural region, a structural body; selectively removing the first sacrificial region thus suspending the structural body on the driving electrode.

Abstract: A method for manufacturing a PMUT device including a piezoelectric element located at a membrane element is provided. The method includes receiving a silicon on insulator substrate having a first silicon layer, an oxide layer, and a second silicon layer. Portions of a first surface of the second silicon layer are exposed by removing exposed side portions of the first silicon layer and corresponding portions of the oxide layer, and a central portion including the remaining portions of the first silicon layer and of the oxide layer is defined. Anchor portions for the membrane element are formed at the exposed portions of the first surface of the second silicon layer. The piezoelectric element is formed above the central portion, and the membrane element is defined by selectively removing the second layer and removing the remaining portion of the oxide from under the remaining portion of the first silicon layer.

Abstract: An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.