Patents Assigned to STMicroelectronics AS
  • Patent number: 9691871
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 27, 2017
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Pierre Caubet, Florian Domengie, Carlos Augusto Suarez Segovia, Aurelie Bajolet, Onintza Ros Bengoechea
  • Patent number: 9691493
    Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 27, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Design and Application S.R.O.
    Inventors: Marco Pasotti, Fabio De Santis, Roberto Bregoli, Dario Livornesi, Sandor Petenyi
  • Patent number: 9688531
    Abstract: A micro-electro-mechanical device formed in a monolithic body of semiconductor material accommodating a first buried cavity; a sensitive region above the first buried cavity; and a second buried cavity extending in the sensitive region. A decoupling trench extends from a first face of the monolithic body as far as the first buried cavity and laterally surrounds the second buried cavity. The decoupling trench separates the sensitive region from a peripheral portion of the monolithic body.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorenzo Baldo, Enri Duqi, Flavio Francesco Villa
  • Patent number: 9691866
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • Patent number: 9689924
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 27, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • Patent number: 9693138
    Abstract: A circuit may include an audio amplifier (314) configured to amplify an input signal (SAUDIO) to generate an output signal (SOUT+, SOUT?) suitable for driving a loud speaker (316). A first circuit (318) may be configured to generate a first analog signal (SI) based on a current level drawn by the loud speaker (316), and a second circuit (320) may be configured to generate a second analog signal (SV) based on a voltage supplied across the loud speaker (316). A third circuit (322, 312) may be configured to generate a third analog signal (RESIDUE) based on the difference between the first and second analog signals, and modify the input signal (SAUDIO) based on the third analog signal.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Alps) SAS
    Inventors: Christian Fraisse, Angelo Nagari
  • Patent number: 9689824
    Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 27, 2017
    Assignee: STMICROELECTRONICS PTE LTD.
    Inventors: Olivier Le Neel, Ravi Shankar, Suman Cherian, Calvin Leung, Tien-Choy Loh, Shian-Yeu Kam
  • Patent number: 9689659
    Abstract: The disclosure relates to a method of detecting an object using a detection signal supplied by a proximity sensor. The method comprises the steps of generating a reference signal by filtering the value of the detection signal, defining a first detection threshold, and going from an object non-detecting state to an object detecting state when the value of the detection signal becomes greater than the first detection threshold. When the value of the detection signal becomes greater than the first detection threshold, the value of the reference signal is readjusted in a manner such that the value of the detection signal again becomes less than or respectively greater than, the first detection threshold.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Maxime Teissier, Cyril Troise
  • Patent number: 9692672
    Abstract: A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 27, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Salvatore Pisasale
  • Patent number: 9689657
    Abstract: The disclosure relates to a method of detecting an object using a detection signal supplied by a proximity sensor. The method comprises the steps of generating a reference signal by filtering the value of the detection signal, defining a first detection threshold, and going from an object non-detecting state to an object detecting state when the value of the detection signal becomes greater than the first detection threshold. When the value of the detection signal becomes greater than the first detection threshold, the value of the reference signal is readjusted in a manner such that the value of the detection signal again becomes less than or respectively greater than, the first detection threshold.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 27, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Maxime Teissier, Cyril Troise
  • Publication number: 20170176577
    Abstract: A ranging apparatus includes a first array with first light sensitive detectors configured to receive light which has been reflected by an object and generate an output. A second array, spaced apart from the first array by a spacing distance, is further included, the second array having second light sensitive detectors. The second array is configurable to either receive light which has been reflected by the object or to be a reference array and generate an output. A processor operates to determine a distance to the object in response to the outputs from the first and the second arrays.
    Type: Application
    Filed: May 11, 2016
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventor: William Halliday
  • Publication number: 20170178744
    Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.
    Type: Application
    Filed: March 1, 2017
    Publication date: June 22, 2017
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ignazio Bruno Mirabella, Salvatore Pappalardo, Calogero Ribellino, Alessandro Nicolosi
  • Publication number: 20170179113
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
    Type: Application
    Filed: April 20, 2016
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez
  • Publication number: 20170179104
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Application
    Filed: April 25, 2016
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Ayres, Bertrand Borot
  • Publication number: 20170176546
    Abstract: A method includes acquiring magnetic data from a magnetometer, processing the magnetic data to perform robust calibration, and generating optimum calibration parameters using a calibration status indicator. To that end, the method includes generating a calibration status indicator as a function of time elapsed since a last calibration and variation in total magnetic field in previously stored magnetic data, detecting anomalies, and extracting a sparse magnetic data set using comparison between the previously stored magnetic data and the magnetic data. Calibration parameters are generated for the magnetometer using a calibration method as a function of the magnetic data set. The calibration parameters are stored based on performing a validation and stability check on the calibration parameters, and weighted with the previously stored calibration parameters to produce weighted calibration parameters.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicants: STMicroelectronics International N.V., STMicroelectronics, Inc.
    Inventors: Mahaveer Jain, Mahesh Chowdhary
  • Publication number: 20170177136
    Abstract: An electronic device disclosed herein includes a touch screen controller to identify an island i.e., a matrix of acquired touch data values, the island including adjacent touch data values indicating a potential touch of a touch sensitive screen. A first sharpness of the island is calculated using a first normalization type and not a second normalization type. A second sharpness of the island is calculated using the first and second normalization types if the first sharpness is greater than the sharpness threshold. A dynamic variance threshold is determined as a function of the second sharpness. A dynamic strength threshold is determined as a function of the second sharpness if a variance of the island is greater than the dynamic variance threshold, and the island is determined to be a valid stylus island if the peak strength is greater than the dynamic strength threshold.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Praveesh Chandran, Manivannan Ponnarasu, Mythreyi Nagarajan
  • Publication number: 20170179250
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Pierre Caubet, Florian Domengie, Carlos Augusto Suarez Segovia, Aurelie Bajolet, Onintza Ros Bengoechea
  • Publication number: 20170176334
    Abstract: Photoluminescence from a sample detector is detected using an array of photo-sensitive detectors. At least one first photo-sensitive detector of the array is provided with a first type of linear polarization filter and at least one second photo-sensitive detector is provided with a second type of linear polarization filter. The first type of linear polarization filter has a plane of polarization which is at angled with respect to a plane of polarization of said second type of polarization filter.
    Type: Application
    Filed: May 10, 2016
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Research & Development) Ltd.
    Inventors: Francescopaolo Mattioli Della Rocca, John Kevin Moore
  • Publication number: 20170179247
    Abstract: An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.
    Type: Application
    Filed: March 9, 2017
    Publication date: June 22, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Julien Delalleau, Christian Rivero
  • Publication number: 20170179196
    Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 22, 2017
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Laurent GRENOUILLET, Sotirios Athanasiou, Philippe Galy