Abstract: A distance sensing apparatus includes a light source configured to emit polarized light. A light sensitive detector detects light emitted by said light source and reflected from a target. The light sensitive detector is configured to substantially prevent polarized light reflected from a target with a relatively high reflectance from being detected.

Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by a chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is coplanar with the upper surface of the substrate. Two such structures are then direct bonded to each other (copper to copper) with opposite areas having a same topology.

Abstract: A ranging apparatus includes an array of light sensitive detectors configured to receive light from a light source which has been reflected by an object. The array includes a number of different zones. Readout circuitry including at least one read out channel is configured to read data output from each of the zones. A processor operates to process the data output to determine position information associated with the object.

Abstract: A sense amplifier enable signal generating circuit includes an input coupled to a dummy bit line of a memory. A voltage comparator circuit compares a voltage on the dummy bit line to a threshold voltage and generates an output signal when the voltage falls below that threshold voltage. A multi-bit counter circuit counts a count value in response to the output signal. A pull-up circuit pulls up the voltage on the dummy bit line in response to the output signal. A count comparator circuit compares the count value to a count threshold and generates a sense amplifier enable signal when the count value equals the count threshold.

Abstract: A transistor device is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at a position where a gate is to be located. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are then converted into a transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are converted into a transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

Abstract: A photodiode structure is based on the use of a double junction sensitive to different wavelength bands based on a magnitude of a reverse bias applied to the photodiode. The monolithic integration of a sensor with double functionality in a single chip allows realization of a low cost ultra-compact sensing element in a single packaging useful in many applications which require simultaneous or spatially synchronized detection of optical photons in different spectral regions.

Abstract: A method supplies power from a power source to a load. The method includes, in a first mode, electrically coupling a step-down converter node of a step-down converter alternately to the power source via a conductive bypass path that bypasses a step-up converter and to ground. The step-up converter has an input electrically coupled to the power source and the step-down converter has an output electrically coupled to the load. The method further includes, in a second mode, coupling the step-down converter node alternately to the power source via the bypass path and to an output of the step-up converter.

Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.

Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.

Abstract: An integrated circuit includes a vertical Shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein. The vertical transistor is formed by, also from top to bottom, a portion of the second region and a fourth region of the second conductivity type. The third and fourth regions are electrically connected to each other.

Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.

Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer above the photodiode, a dielectric region above the antireflection layer and an optical filter to pass incident luminous radiation having a given wavelength. The antireflection layer may include an array of pads mutually separated by a dielectric material of the dielectric region. The array may be configured to allow simultaneous transmission of the incident luminous radiation and a diffraction of the incident luminous radiation producing diffracted radiations which have wavelengths below that of the incident radiation, and are attenuated with respect to the incident radiation.

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract: A method for securing a data processing system having a processing unit is disclosed. At least a group of N1 digital words of m1 bits is selected from among the set of M1 digital words. N1 is less than M1. These words are selected in such a way that each selected digital word differs from all the other selected digital words by a number of bits at least equal to an integer p which is at least equal to 2. The group of N1 digital words of m1 bits form at least one group of N1 executable digital instructions. The processing unit is configured to make it capable of executing each instruction of the at least one group of N1 executable digital instructions.

Abstract: A detector of an event includes an electrical energy generator formed by a flexible piezoelectric element with a weight fastened to the flexible piezoelectric element that is biased with the weight in a position with the piezoelectric element flexed. In response to detection of the event, a trigger releases the weight so as to cause a vibration of the piezoelectric element. This vibration is converted by the flexible piezoelectric element into electrical energy. An electronic system is power by the electrical energy and is operable to generate an electrical signal indicative of the detected event.

Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

Abstract: A driver circuit includes a high-side power transistor having a source-drain path coupled between a first node and a second node and a low-side power transistor having a source-drain path coupled between the second node and a third node. A high-side drive circuit, having an input configured to receive a drive signal, includes an output configured to drive a control terminal of said high-side power transistor. The high-side drive circuit is configured to operate as a capacitive driver. A low-side drive circuit, having an input configured to receive a complement drive signal, includes an output configured to drive a control terminal of said low-side power transistor. The low-side drive circuit is configured to operate as a level-shifting driver.

Abstract: An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.