Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.
Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
Type:
Application
Filed:
March 28, 2017
Publication date:
July 13, 2017
Applicant:
STMicroelectronics S.r.l.
Inventors:
Marcella Carissimi, Marco Pasotti, Fabio De Santis
Abstract: A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a supporting structure, the supporting structure being of a soluble type. A chip including a semiconductor body is mechanically coupled to the supporting structure. The sinterable material is sintered such that each preliminary contact region forms a corresponding sintered preliminary contact, and the chip and the plurality of preliminary contact regions are coated with a dielectric coating region, and the supporting structure is removed using a jet of liquid.
Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.
Abstract: A front-side image sensor may include a substrate in a semiconductor material and an active layer in the semiconductor material. The front side image sensor may also include an array of photodiodes formed in the active layer and an insulating layer between the substrate and the active layer.
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
Abstract: A sensing circuit includes: a follower transistor, having a control terminal; a follower terminal for connection to a load; a bias-current generator, coupled to the follower terminal; and a feedback stage, configured to control the bias-current generator as a function of an input signal on the control terminal of the follower transistor.
Abstract: Embodiments include a method and an apparatus for the localization of at least one source of an acoustic signal including: temporally sampling the acoustic signal with a plurality of microphones to obtain a (D+1)-dimensional space-time matrix representation of the acoustic signal, wherein D is the number of spatial dimensions, applying a (D+1)-dimensional Fourier transform to the matrix representation, determining a first peak in a spectrum obtained based on the application of the Fourier transform, and calculating the direction of arrival of the acoustic signal at at least one of the plurality of microphones based on the determined first peak.
Abstract: This invention relates to switching power saving modes and rescheduling communication frames for various periods of a beacon interval (BI) defined under WGA Draft Specification 0.8 for the personal basic service set (PBSS) and infrastructure BSS to achieve further power savings and other advantages. Stations can be awake during a contention-based period (CBP) if it is in active state and can schedule frames during a service period (SP) to allow the assigned receiver to transmit to the assigned initiator. Stations in a group can schedule a group address frame to be sent during the CBP and group SP of a specific periodic BI. Stations in peer-to-peer connection may directly notify its peer stations of its power saving mode and wakeup schedule. Stations of an infrastructure basic service set (BSS) can also use the same power saving mechanism as stations of a PBSS noting a difference where each BI will be an access point's (AP's) awake BI.
Abstract: An image sensor includes a first photodiode with associated first sense node and a second photodiode with associated second sense node. A first transistor has its control node coupled to the first sense node and a second transistor has its control node coupled to the second sense node. The conduction paths (for example, source-drain paths) of the first and second transistors are coupled in series between first and second column lines associated with a column of the image sensor array. Switches control connection of the first and second column lines in two modes: one mode where a voltage is applied to the first column line and data from one of the photodiodes is read out by the second column line; and another mode where a voltage is applied to the second column line and data from the other of the photodiodes is read out by the first column line.
Abstract: An active stylus is capacitively coupled to a capacitive touch panel for communication. The active stylus operates in a wait mode to receive initial communications from the panel. In response to such receipt, the active stylus synchronizes to a repeating communications frame implementing time division multiplexing. Communications from the active stylus to the panel include: information communications; synchronization communications and communications specific for columns and/or rows of the panel. Communications from the panel to the active stylus may be addressed uniquely to the stylus or commonly to a group of styluses.
Type:
Grant
Filed:
August 18, 2014
Date of Patent:
July 11, 2017
Assignee:
STMICROELECTRONICS ASIA PACIFIC PTE LTD
Inventors:
Praveesh Chandran, Baranidharan Karuppusamy, Giuseppe Noviello, Chee Weng Cheong, Leonard Dinu, Dianbo Guo, Kien Beng Tan, Chaochao Zhang
Abstract: The device is equipped with several protocol decoding means (DCDi) corresponding respectively to various communication protocols so as to be capable of dialoguing with the said communication apparatus during transactions selectively according to one of these communication protocols; the method comprises an automatic protocol detection comprising a) an activation (40) of all the decoding means at the start of a transaction, b) a delivery of the signal received by the electronic device to all the decoding means, c) an analysis (41) of at least one signal delivered by at least one of the decoding means and d) a selection (42) of one of the decoding means on the basis of the result of the said analysis, and a conducting of the said transaction with the selected decoding means.
Type:
Grant
Filed:
November 8, 2016
Date of Patent:
July 11, 2017
Assignee:
STMicroelectronics (Rousset) SAS
Inventors:
Frederic Bancel, Nathalie Link, Brigitte Hennebois, David Chomaud
Abstract: An electronic device includes a circuit integrated on a die having front and back surfaces with die terminals on the front surface. The die is embedded in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.
Type:
Grant
Filed:
June 8, 2015
Date of Patent:
July 11, 2017
Assignee:
STMICROELECTRONICS S.R.L.
Inventors:
Fulvio Vittorio Fontana, Giovanni Graziosi
Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.
Abstract: An integrated circuit (IC) may include a semiconductor substrate, and a semiconductor resistor. The semiconductor resistor may include a well in the semiconductor substrate and having a first conductivity type, a first resistive region in the well having an L-shape and a second conductivity type, and a tuning element associated with the first resistive region. The IC may also include a resistance compensation circuit on the semiconductor substrate. The resistance compensation circuit may be configured to measure an initial resistance of the first resistive region, and generate a voltage at the tuning element to tune an operating resistance of the first resistive region based upon the measured initial resistance.
Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).
Type:
Grant
Filed:
September 9, 2016
Date of Patent:
July 11, 2017
Assignees:
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
Abstract: A method of pairing an intelligent input device with an electronic device includes transmitting a start pairing identifier and receiving a unique identifier that identifies the intelligent input device. The method further includes authenticating the unique identifier using authentication information stored in the electronic device and transmitting a pairing successful identifier responsive to the unique identifier being authenticated to thereby pair the intelligent input device and the electronic device.
Abstract: The present disclosure is directed to a switching power converter having a regulated output voltage or output current. The power converter uses a control unit having a signal conditioning circuit to produce a control voltage signal, which is used to drive a power stage of the converter. The signal conditioning circuit includes a comparator that compares a measured electrical quantity to a reference value representative of a desired regulated output quantity, and produces a digital detection signal based on the comparison. A control actuator uses the digital detection signal to produce a correction signal, which is received by an averaging circuit. The averaging circuit then produces the control voltage signal based on an average of the correction signal.
Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.
Type:
Application
Filed:
December 28, 2016
Publication date:
July 6, 2017
Applicants:
STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventors:
Francois Roy, Boris Rodrigues, Marie Guillon, Yvon Cazaux, Benoit Giffard