Abstract: A driving apparatus configured to drive a light emitting device includes a driving current source module operable to supply current to the light emitting device via a node during operation. A protection module coupled to the node and the driving current source module selectively injects current to the node during operation. The driving current source module is controlled based on a detection result of a voltage on the node.

Abstract: A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract: Multiple virtual MAC addresses may be added to WGA devices that may have different traffic streams to another device that requires different services, thus creating distinct MAC and device level implications. Beamforming training can be done at the device level for all virtual MAC addresses. Wakeup, doze, and ATIM power save can be done at the device level depending on the frames received. Authentication, deauthentication, association, and deassociation can be done variously at both levels. Further MSDUs can be aggregated for the multiple MAC addresses.

Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

Abstract: In one embodiment of the present invention, a method is provided for performing motion compensated interpolation using a previous frame and a current frame of a displayable output, the method comprising: detecting the speed of an object in the displayable output relative to the speed of a background in the displayable output; and blending results from a halo reducing interpolator and a median interpolator, wherein the results of each of the interpolators are weighted based on the speed of the object, to arrive at an interpolated frame using the previous frame and the current frame.

Abstract: A method is for managing information communication between an NFC controller coupled to an antenna for a contactless communication with an object, a device host, and a secure element. The method may include routing the information through the NFC controller, and communicating first information to be communicated between the secure element and the device host through a first communication link between the NFC controller and the device host, and through a second communication link between the NFC controller and the secure element. The method may include communicating second information with the antenna through a third communication link between the NFC controller and the secure element, the first and second communication links having bandwidths greater than a bandwidth of the third communication link.

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.

Abstract: A switching amplifier includes a first half-bridge PWM modulator, a second half-bridge PWM modulator, and at least one amplifier stage configured to receive input signals. The switching amplifier also includes a PWM control stage configured to control switching of the first PWM modulator and of the second PWM modulator as a function of the input signals, by respective first PWM control signals and second PWM control signals. The amplifier stage and the PWM control stage have a fully differential structure.

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Abstract: Detecting the presence of a finger in proximity of a screen that generates detection signals in the horizontal direction and vertical direction includes sampling the detection signals and generating raw-data vectors X and Y. The raw data have a maximum for elements of the vector that define the position of the finger on the screen in the directions X and Y, respectively. The vectors X and Y are divided into subsets defined as “macro-areas” and cumulative values computed of each macro-area by adding together all the elements of the vector X and of the vector Y that belong to the macro-area. The maximum values are selected from among horizontal cumulative values and vertical cumulative values. A value identifying the macro-area selected on the basis of the maximum values is supplied, or no value supplied in the presence of elements of disturbance in the proximity of the screen.

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Abstract: An integrated circuit includes SOI-type MOS transistors on insulator, with a first well capable of being biased located under the insulator. The first wells are doped with a first conductivity type. Each first well includes, under the insulator of each transistor, a back gate region that is more heavily doped than the first well. The first wells are separated from each other by inclusion in in a second well that is also capable of being biased. The second well is doped with a second conductivity type.

Abstract: A diagnostic device includes a photodiode formed by a body of semiconductor material having a first surface, an integrated optical structure on the first surface and having a second surface, and at least one detection region on the second surface. The at least one detection region includes at least one receptor that binds to a corresponding target molecule that can be mated with a corresponding marker, which, when excited by radiation having a first wavelength, emits radiation having a second wavelength that can be detected by the photodiode. The integrated optical structure includes at least a first layer of a first material having a first refractive index. The first layer has a thickness substantially equal to an integer and odd multiple of one fourth of the first wavelength divided by the first refractive index.

Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Abstract: An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.

Abstract: A circuit includes a force driver configured to apply a force signal to a force node associated with a mutual capacitance to be sensed. A sensing circuit receives a sense signal from a sense node associated with said mutual capacitance to be sensed. The sensing circuit operates to generate an output signal indicative of the sensed mutual capacitance. A control circuit controls generation of the force signal to alternate between at least two different frequencies and generate said output signal for each half cycle of the force signal.

Abstract: A hybrid analog-digital pixel circuit is fabricated on two wafers. A first wafer includes the analog pixel circuitry and a second wafer includes the digital control and processing circuitry. Externally accessible contact structures for electrically interconnecting the two wafers are arranged in groups. Each group includes externally accessible contact structures for carrying signals associated solely with operation of a corresponding pixel.

Abstract: A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface.

Abstract: A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface.