Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Publication number: 20210057521
    Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • Publication number: 20210057426
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto PIAZZA, Sebastien LAGRASTA, Raul Andres BIANCHI, Simon JEANNOT
  • Publication number: 20210057520
    Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • Publication number: 20210050224
    Abstract: An electrode is included in a base substrate. A trench is produced in the base substrate. The trench is filled with an annealed amorphous material to form the electrode. The electrode is made of a crystallized material which includes particles that are implanted into a portion of the electrode that is located adjacent the front-face side of the base substrate.
    Type: Application
    Filed: August 11, 2020
    Publication date: February 18, 2021
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Joel SCHMITT, Bilel SAIDI, Sylvain JOBLOT
  • Patent number: 10924700
    Abstract: A pixel of an imager device includes a photosensitive area configured to integrate a light signal. A first capacitive storage node is configured to receive a signal representative of the number of charges generated by the photosensitive area. A second capacitive storage node is configured to receive a reference signal. A first transfer transistor is coupled between the first capacitive storage node and the photosensitive area. A second transfer transistor is coupled between the second capacitive storage node and a terminal which supplied the reference signal. The first and second two transfer transistors have a common conduction electrode and a common substrate, wherein the common substrate is coupled to the first capacitive storage node.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: February 16, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Pierre Malinge
  • Patent number: 10921370
    Abstract: The invention concerns an optoelectronic chip including a pair of optical inputs having a same bandwidth, and each being adapted to a different polarization, at least one photonic circuit to be tested, and an optical coupling device configured to couple the two inputs to the circuit to be tested.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 16, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Patrick Le Maitre, Jean-Francois Carpentier
  • Patent number: 10914896
    Abstract: An elementary photonic interconnect switch is integrated into an optoelectronic chip and includes four simple photonic interconnect switches. Each simple photonic interconnect switch has two optical waveguides that cross and are linked by a ring resonator having one ring. A basic photonic interconnect switch, a complex photonic interconnect switch and/or a photonic interconnect network are integrated into an optoelectronic chip and including at least two elementary photonic interconnect switches.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 9, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Michit, Patrick Le Maitre
  • Patent number: 10910428
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 2, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Sonarith Chhun
  • Patent number: 10903423
    Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 26, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Pierre Morin, Michel Haond, Paola Zuliani
  • Patent number: 10903259
    Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. Each pixel includes an active photosensitive area formed in a portion of the semiconductor layer laterally delimited by peripheral insulating walls. The pixels include a first pixel of a first type and a second pixel of a second type. The portion of semiconductor layer of the first pixel has a first lateral dimension selected to define a lateral cavity resonating at a first wavelength and the portion of semiconductor layer of the second pixel has a second lateral dimension different from the first lateral dimension. The second lateral dimension is selected to define a lateral cavity resonating at a second wavelength different from the first wavelength.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: January 26, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Denis Rideau, Axel Crocherie
  • Patent number: 10903174
    Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a back side of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the back side of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the back side, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 26, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Sebastien Petitdidier
  • Patent number: 10892291
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith Chhun, Gregory Imbert
  • Patent number: 10892292
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
  • Publication number: 20200411381
    Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Gregory AVENIER, Alexis GAUTHIER, Pascal CHEVALIER
  • Publication number: 20200411657
    Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali GREGOIRE
  • Publication number: 20200411382
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
  • Patent number: 10877211
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Publication number: 20200403154
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier HINSINGER
  • Publication number: 20200400978
    Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Stephane MONFRAY
  • Patent number: 10871663
    Abstract: A device, includes: a ring waveguide; a diode comprising a junction extending at least partly in the ring waveguide; and a first circuit configured to supply a signal representative of a leakage current in the diode.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 22, 2020
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ETAUX ENERGIES ALTERNATIVES
    Inventors: Patrick Le Maitre, Nicolas Michit, Jean-Francois Carpentier, Benoit Charbonnier