Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Publication number: 20220310867
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 29, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin ZIMMER, Dominique GOLANSKI, Raul Andres BIANCHI
  • Publication number: 20220308190
    Abstract: An indirect time-of-flight (iTOF) includes a pixel with a photoconversion area, a readout circuit and at least two circuit sets. Each circuit set includes: a capacitive element connected to a first node of the circuit set; a controllable charge transfer device connected between a first electrode of the photoconversion area and the first node; and a first transistor having a gate connected to the first node, a source connected to the readout circuit and a drain configured to receive a bias potential. The capacitive element is configured to store a voltage in response to charges generated by the photoconversion area.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 29, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Matteo Maria VIGNETTI, Pierre MALINGE
  • Patent number: 11454669
    Abstract: An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 27, 2022
    Assignees: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Manoj Kumar, Lionel Courau, Geeta, Olivier Le-Briz
  • Patent number: 11451730
    Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: September 20, 2022
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Crolles2) SAS
    Inventors: Pierre Malinge, Frederic Lalanne, Laurent Simony
  • Patent number: 11444110
    Abstract: A pixel includes a photoconversion zone, an insulated vertical electrode and at least one charge storage zone. The photoconversion zone belongs to a first part of a semiconductor substrate and each charge storage zone belongs to a second part of the substrate physically separated from the first part of the substrate by the insulated vertical electrode.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: September 13, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Boris Rodrigues Goncalves, Frederic Lalanne
  • Publication number: 20220268965
    Abstract: An optical device includes a layer having a face configured to be traversed by light at an operating wavelength. The face of the layer includes a fractal structure lacking rotational symmetry such as a fractal structure that corresponds to a fractal expressed in an L-system. The fractal structure is formed by recesses that penetrate into the layer from the face. The recesses have a depth which is less that a thickness of the layer.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 25, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Arthur ARNAUD
  • Patent number: 11417789
    Abstract: An electronic device is provided that includes a photodiode. The photodiode includes a semiconductor region coupled to a node of application of a first voltage, and at least one semiconductor wall. The at least one semiconductor wall extends along at least a height of the photodiode and partially surrounds the semiconductor region.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 16, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Arnaud Tournier, Boris Rodrigues Goncalves, Francois Roy
  • Patent number: 11417756
    Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: August 16, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Edoardo Brezza, Alexis Gauthier, Fabien Deprat, Pascal Chevalier
  • Publication number: 20220254905
    Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean JIMENEZ MARTINEZ
  • Publication number: 20220254686
    Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Gregory AVENIER, Alexis GAUTHIER, Pascal CHEVALIER
  • Publication number: 20220254879
    Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 11, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
  • Patent number: 11411177
    Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: August 9, 2022
    Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
  • Patent number: 11398549
    Abstract: Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 26, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Nicolas Guitard
  • Patent number: 11398521
    Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: July 26, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
  • Publication number: 20220231483
    Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Mathias PROST, Moustafa EL KURDI, Philippe BOUCAUD, Frederic BOEUF
  • Patent number: 11391624
    Abstract: A light sensor includes a first pixel and a second pixel. Each pixel has a photoconversion area. A band-stop Fano resonance filter is arranged over the first pixel. The second pixel includes no Fano resonance filter. Signals output from the first and second pixels are processed to determine information representative of the quantity of light received by the light sensor during an illumination phase in a rejection band of the band-stop Fano resonance filter.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: July 19, 2022
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Le Neel, Stephane Monfray
  • Patent number: 11387195
    Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a backside of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the backside of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the backside, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 12, 2022
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Sebastien Petitdidier
  • Patent number: 11387379
    Abstract: A semiconductor layer is doped with a first doping type and has an upper surface. A first electrode insulated from the semiconductor layer extending through the semiconductor layer from the upper surface. A second electrode insulated from the semiconductor layer extends through the semiconductor layer from the upper surface. The first and second electrodes are biased by a voltage to produce an electrostatic field within the semiconductor layer causing the formation of a depletion region. The depletion region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at first and second oppositely doped regions within the semiconductor substrate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 11378827
    Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 5, 2022
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Stephane Monfray, Frédéric Boeuf
  • Publication number: 20220199648
    Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 23, 2022
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier WEBER, Christophe LECOCQ