Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Publication number: 20190312170
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Application
    Filed: December 17, 2018
    Publication date: October 10, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • Publication number: 20190312039
    Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon, Bastien Giraud
  • Publication number: 20190296007
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean JIMENEZ
  • Publication number: 20190285802
    Abstract: An optical waveguide termination device includes a waveguide and metal vias surrounding an end portion of the waveguide. The end portion of the waveguide has a transverse cross-sectional area that decreases towards its distal end. The metal vias are orthogonal to a same plane, with the same plane being orthogonal to the transverse cross-section. The metal vias absorb light originating from the end portion when a light signal propagates through the waveguide, and the metal vias and the end portion provide that an effective index of an optical mode to be propagated through the waveguide progressively varies in the end portion. Additional metal vias may be present along the waveguide upstream of the end portion, with the additional metal vias bordering the waveguide upstream of the end portion providing that the effective index of an optical mode to be propagated through the waveguide varies progressively toward the end portion.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain GUERBER, Charles BAUDOT
  • Publication number: 20190285694
    Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 19, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent HUARD, Chittoor PARTHASARATHY
  • Publication number: 20190287862
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoit FROMENT, Stephan NIEL, Arnaud REGNIER, Abderrezak MARZAKI
  • Publication number: 20190285799
    Abstract: An optical waveguide is configured to propagate a light signal. Metal vias are arranged along and on either side of a portion of the optical waveguide. Additional metal vias are further arranged along and on either side of the optical waveguide both upstream and downstream of the portion of the optical waveguide. The metal vias and additional metal vias are oriented orthogonal to a same plane, the same plane being orthogonal to a transverse cross-section of the portion of the optical waveguide.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 19, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain GUERBER, Charles BAUDOT
  • Patent number: 10418486
    Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 17, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Francois Andrieu
  • Publication number: 20190280146
    Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles BAUDOT, Sebastien CREMER, Nathalie VULLIET, Denis PELLISSIER-TANON
  • Publication number: 20190280144
    Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles BAUDOT, Sebastien CREMER, Nathalie VULLIET, Denis PELLISSIER-TANON
  • Publication number: 20190280032
    Abstract: An integrated image sensor with backside illumination includes a pixel. The pixel is formed by a photodiode within an active semiconductor region having a first face and a second face. A converging lens, lying in front of the first face of the active region, directs received light rays towards a central zone of the active region. At least one diffracting element, having a refractive index different from a refractive index of the active region, is provided at least partly aligned with the central zone at one of the first and second faces.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Axel CROCHERIE, Pierre Emmanuel Marie MALINGE
  • Publication number: 20190280024
    Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10401571
    Abstract: The disclosure relates to an optical splitter including two waveguides on either side of an axis. Each waveguide includes a first segment and a second segment that are closer to the axis than the rest of the waveguide. The first segments are optically coupled and the second segments are optically coupled. Each guide includes between the first and second segment, starting from the first segment, a first curved section including in succession a curvature the concavity of which is turned the side opposite the axis then a curvature the concavity of which is turned towards the axis, and starting from the second segment a second curved section including in succession a curvature the concavity of which is turned the side opposite the axis then a curvature the concavity of which is turned towards the axis. The first curved sections of the two waveguides are curved differently.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Patrick Le Maitre, Jean-Francois Carpentier
  • Patent number: 10403682
    Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Morin, Philippe Brun, Laurent-Luc Chapelon
  • Publication number: 20190267335
    Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.
    Type: Application
    Filed: February 18, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier DUTARTRE
  • Publication number: 20190267473
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Guillaume C. RIBES
  • Patent number: 10393958
    Abstract: A method for making an electro-optic device includes forming a first photonic device having a first material in a first photonic layer over a substrate layer. A second photonic layer with a second photonic device is formed over the first photonic layer and includes a second material different than the first material. A dielectric layer is formed over the second photonic layer. A first electrically conductive via extending through the dielectric layer and the second photonic layer is formed so as to couple to the first photonic device. A second electrically conductive via extending through the dielectric layer and coupling to the second photonic device is formed. A third electrically conductive via extending through the dielectric layer, the second photonic layer, and the first photonic layer is formed so as to couple to the substrate layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: August 27, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Frédéric Boeuf, Charles Baudot
  • Patent number: 10393965
    Abstract: A photonic interconnection elementary switch is integrated in an optoelectronic chip/The switch includes first and second linear optical waveguides which intersect to form a first intersection. Two first photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. Two second photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. A third linear optical waveguide is coupled to one of the first ring resonators and one of the second ring resonators. A fourth linear optical waveguide is coupled to another of the first resonators and to another of the second ring resonators. A base switch, complex switch, and photonic interconnection network integrated in an optoelectronic chip, include at least two of the photonic interconnection elementary switches.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Michit, Patrick Le Maitre
  • Patent number: 10397503
    Abstract: A photodiode produces photogenerated charges in response to exposure to light. An integration period collects the photogenerated charges. Collected photogenerated charges in excess of an overflow threshold are passed to an overflow sense node. Remaining collected photogenerated charges are passed to a sense node. A first signal representing the overflow photogenerated charges is read from the overflow sense node. A second signal representing the remaining photogenerated charges is read from the sense node.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Emmanuel Marie Malinge, Frederic Lalanne
  • Publication number: 20190259838
    Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Julien BORREL