Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Patent number: 12224302
    Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 11, 2025
    Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Jeff M. Raynor, Frederic Lalanne, Pierre Malinge
  • Patent number: 12218163
    Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.
    Type: Grant
    Filed: February 29, 2024
    Date of Patent: February 4, 2025
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael Fourel, Laurent-Luc Chapelon
  • Publication number: 20250039577
    Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.
    Type: Application
    Filed: October 11, 2024
    Publication date: January 30, 2025
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic LALANNE, Pierre MALINGE
  • Patent number: 12211754
    Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: January 28, 2025
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
    Inventors: Pierpaolo Monge Roffarello, Isabella Mica, Didier Dutartre, Alexandra Abbadie
  • Patent number: 12199131
    Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 14, 2025
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Gay, Frederic Lalanne, Yann Henrion, Francois Guyader, Pascal Fonteneau, Aurelien Seignard
  • Patent number: 12176030
    Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.
    Type: Grant
    Filed: December 11, 2023
    Date of Patent: December 24, 2024
    Assignees: Universite D'Aix Marseille, Centre National de la Recherche, STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Michel Portal, Vincenzo Della Marca, Jean-Pierre Walder, Julien Gasquez, Philippe Boivin
  • Patent number: 12167703
    Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: December 10, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy Berthelon, Franck Arnaud
  • Publication number: 20240405146
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin ZIMMER, Dominique GOLANSKI, Raul Andres BIANCHI
  • Patent number: 12147105
    Abstract: A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: November 19, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Sebastien Cremer
  • Publication number: 20240380999
    Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois ROY, Thomas DALLEAU
  • Patent number: 12143743
    Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 12, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic Lalanne, Pierre Malinge
  • Patent number: 12144187
    Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: November 12, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Remy Berthelon, Olivier Weber
  • Patent number: 12140799
    Abstract: A ring resonator electro-optical device includes a first silicon nitride waveguide and a second annular silicon waveguide that comprises a first section running under a second section of the first waveguide. The second waveguide also includes an annular silicon strip having a cross-section increasing in the first section from a minimum cross-section located under the second section.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 12, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Patrick Le Maitre, Nicolas Michit
  • Patent number: 12123910
    Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: October 22, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Patrick Le Maitre, Jean-Francois Carpentier
  • Patent number: 12125894
    Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: October 22, 2024
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics France
    Inventors: Alexis Gauthier, Pascal Chevalier
  • Publication number: 20240339464
    Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 10, 2024
    Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
  • Publication number: 20240332324
    Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • Patent number: 12087708
    Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Petitdidier, Nicolas Hotellier, Raul Andres Bianchi, Alexis Farcy, Benoit Froment
  • Patent number: 12087873
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin Zimmer, Dominique Golanski, Raul Andres Bianchi
  • Patent number: 12075178
    Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: August 27, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Thomas Dalleau