Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

Abstract: A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.

Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.

Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls.

Abstract: A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.

Abstract: A method includes forming a layer made of a first insulating material on a first layer made of a second insulating material that covers a support, defining a waveguide made of the first material in the layer of the first material, covering the waveguide made of the first material with a second layer of the second material, planarizing an upper surface of the second layer of the second material, and forming a single-crystal silicon layer over the second layer.

Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.

Abstract: A ring resonator electro-optical device includes a first silicon nitride waveguide and a second annular silicon waveguide that comprises a first section running under a second section of the first waveguide. The second waveguide also includes an annular silicon strip having a cross-section increasing in the first section from a minimum cross-section located under the second section.

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

Abstract: An optoelectronic chip includes optical inputs having different passbands, a photonic circuit to be tested, and an optical coupling device configured to couple said inputs to the photonic circuit to be tested.