Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Patent number: 10804112
    Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Loic Gaben
  • Patent number: 10794856
    Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Getenet Tesega Ayele, Stephane Monfray
  • Patent number: 10795189
    Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Stephane Monfray
  • Patent number: 10797234
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier Hinsinger
  • Publication number: 20200303423
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Application
    Filed: June 11, 2020
    Publication date: September 24, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Jean-Jacques FAGOT, Philippe BOIVIN, Franck ARNAUD
  • Patent number: 10777680
    Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 15, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Francois Andrieu
  • Patent number: 10771048
    Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 8, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Capucine Lecat-Mathieu De Boissac, Fady Abouzeid, Gilles Gasiot, Philippe Roche, Victor Malherbe
  • Patent number: 10770306
    Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Bar, Francois Leverd, Delia Ristoiu
  • Patent number: 10770357
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 8, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoit Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
  • Publication number: 20200266609
    Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
    Type: Application
    Filed: May 6, 2020
    Publication date: August 20, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Mathias PROST, Moustafa EL KURDI, Philippe BOUCAUD, Frederic BOEUF
  • Publication number: 20200266310
    Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 20, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Boris RODRIGUES GONCALVES, Arnaud TOURNIER
  • Publication number: 20200256759
    Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe GROSSE, Patrick LE MAITRE, Jean-Francois CARPENTIER
  • Patent number: 10741740
    Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Emmanuel Dubois, Jean-Francois Robillard, Stephane Monfray, Thomas Skotnicki
  • Patent number: 10741565
    Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 11, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Andrieu, Remy Berthelon, Bastien Giraud
  • Patent number: 10739807
    Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Guenole Lallement, Fady Abouzeid
  • Publication number: 20200252059
    Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.
    Type: Application
    Filed: January 20, 2020
    Publication date: August 6, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Capucine LECAT-MATHIEU DE BOISSAC, Fady ABOUZEID, Gilles GASIOT, Philippe ROCHE, Victor MALHERBE
  • Publication number: 20200241201
    Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic BOEUF, Charles BAUDOT
  • Publication number: 20200233032
    Abstract: A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 23, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Yann CARMINATI
  • Publication number: 20200236320
    Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 23, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic LALANNE, Pierre MALINGE
  • Patent number: 10705294
    Abstract: An optical waveguide termination device includes a waveguide and metal vias surrounding an end portion of the waveguide. The end portion of the waveguide has a transverse cross-sectional area that decreases towards its distal end. The metal vias are orthogonal to a same plane, with the same plane being orthogonal to the transverse cross-section. The metal vias absorb light originating from the end portion when a light signal propagates through the waveguide, and the metal vias and the end portion provide that an effective index of an optical mode to be propagated through the waveguide progressively varies in the end portion. Additional metal vias may be present along the waveguide upstream of the end portion, with the additional metal vias bordering the waveguide upstream of the end portion providing that the effective index of an optical mode to be propagated through the waveguide varies progressively toward the end portion.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: July 7, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Guerber, Charles Baudot