Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Patent number: 10903423
    Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 26, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Pierre Morin, Michel Haond, Paola Zuliani
  • Patent number: 10903259
    Abstract: A multispectral image sensor includes a semiconductor layer and a number of pixels formed inside and on top of the semiconductor layer. Each pixel includes an active photosensitive area formed in a portion of the semiconductor layer laterally delimited by peripheral insulating walls. The pixels include a first pixel of a first type and a second pixel of a second type. The portion of semiconductor layer of the first pixel has a first lateral dimension selected to define a lateral cavity resonating at a first wavelength and the portion of semiconductor layer of the second pixel has a second lateral dimension different from the first lateral dimension. The second lateral dimension is selected to define a lateral cavity resonating at a second wavelength different from the first wavelength.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: January 26, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Denis Rideau, Axel Crocherie
  • Patent number: 10903174
    Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a back side of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the back side of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the back side, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 26, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Sebastien Petitdidier
  • Patent number: 10892292
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
  • Patent number: 10892291
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith Chhun, Gregory Imbert
  • Publication number: 20200411381
    Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Gregory AVENIER, Alexis GAUTHIER, Pascal CHEVALIER
  • Publication number: 20200411657
    Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali GREGOIRE
  • Publication number: 20200411382
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
  • Patent number: 10877211
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Publication number: 20200400978
    Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Stephane MONFRAY
  • Publication number: 20200403154
    Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Olivier HINSINGER
  • Patent number: 10871663
    Abstract: A device, includes: a ring waveguide; a diode comprising a junction extending at least partly in the ring waveguide; and a first circuit configured to supply a signal representative of a leakage current in the diode.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 22, 2020
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ETAUX ENERGIES ALTERNATIVES
    Inventors: Patrick Le Maitre, Nicolas Michit, Jean-Francois Carpentier, Benoit Charbonnier
  • Publication number: 20200388505
    Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 10, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien BORREL, Magali GREGOIRE
  • Patent number: 10861997
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 8, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Publication number: 20200381297
    Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: December 3, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Magali GREGOIRE
  • Patent number: 10833027
    Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: November 10, 2020
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Raul Andres Bianchi, Benoit Froment
  • Patent number: 10833094
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • Patent number: 10830955
    Abstract: A photonic interconnect switch is formed by first and second linear optical waveguides that cross to form an intersection. First and second redirecting photonic ring resonators are coupled together in an intermediate optical coupling zone and are controllable with an electrical signal. The first ring resonator is coupled to the first optical waveguide in a first optical coupling zone. The second ring resonator is coupled to the second optical waveguide in a second optical coupling zone.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 10, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Michit, Patrick Le Maitre
  • Publication number: 20200350355
    Abstract: The present disclosure relates to an image sensor that includes first and second pixels. One or more transistors of the first pixel share an active region with one or more transistors of the second pixel.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 5, 2020
    Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
    Inventors: Jeff M. RAYNOR, Frederic LALANNE, Pierre MALINGE
  • Patent number: 10823986
    Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 3, 2020
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Stephane Monfray, Frédéric Boeuf