Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Patent number: 10707270
    Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: July 7, 2020
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe Boivin, Simon Jeannot
  • Publication number: 20200211835
    Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.
    Type: Application
    Filed: December 10, 2019
    Publication date: July 2, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Delia RISTOIU, Pierre BAR, Francois LEVERD
  • Publication number: 20200203211
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 25, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal GOURAUD, Delia RISTOIU
  • Patent number: 10690947
    Abstract: In one aspect, a photonic device includes a first region having a first doping type, where the first region is divided into an upper portion made of silicon-germanium and a lower portion made of silicon. The device further includes a second region having a second doping type. The first region and the second region contact to form a vertical PN junction.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: June 23, 2020
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Stephane Monfray, Frédéric Boeuf
  • Patent number: 10684251
    Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 16, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Getenet Tesega Ayele, Stephane Monfray
  • Patent number: 10684326
    Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 16, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Clerc, Gilles Gasiot
  • Patent number: 10686297
    Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 16, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mathias Prost, Moustafa El Kurdi, Philippe Boucaud, Frederic Boeuf
  • Publication number: 20200185563
    Abstract: A semiconductor layer is doped with a first doping type and has an upper surface. A first electrode insulated from the semiconductor layer extending through the semiconductor layer from the upper surface. A second electrode insulated from the semiconductor layer extends through the semiconductor layer from the upper surface. The first and second electrodes are biased by a voltage to produce an electrostatic field within the semiconductor layer causing the formation of a depletion region. The depletion region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at first and second oppositely doped regions within the semiconductor substrate.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • Publication number: 20200185562
    Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois ROY
  • Patent number: 10677684
    Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 9, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Grosse, Patrick Le Maitre, Jean-Francois Carpentier
  • Publication number: 20200168646
    Abstract: An integrated imaging device includes a pixel having a trench that extends into the substrate. The trench is coated with an insulator and filled with a stack including a first polysilicon region and a second polysilicon region. The first and second polysilicon regions are separated from each other by a layer of insulating material. The first polysilicon region may form a gate electrode of a vertical transistor and the second polysilicon region may form an electrode of a capacitor.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 28, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Andrej SULER, Francois ROY
  • Patent number: 10656331
    Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Frederic Boeuf, Charles Baudot
  • Patent number: 10658197
    Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: May 19, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Nicolas Posseme, Maxime Garcia-Barros, Yves Morand
  • Patent number: 10658578
    Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10?5 ?·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Morin, Didier Dutartre
  • Publication number: 20200150292
    Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 14, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Gilles GASIOT, Fady ABOUZEID
  • Publication number: 20200150174
    Abstract: An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 14, 2020
    Applicants: STMicroelectronics International N.V., STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Manoj KUMAR, Lionel COURAU, GEETA, Olivier LE-BRIZ
  • Patent number: 10651376
    Abstract: The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28). The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 12, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sophie Bernasconi, Christelle Charpin-Nicolle, Aomar Halimaoui
  • Patent number: 10641868
    Abstract: A sensor array includes pixel kernels, wherein each pixel kernel includes RGB pixels, the RGB pixels being configured to provide a plurality of color signals, and Z pixels each having a single memory element, the Z pixels being configured to provide a single TOF signal. Each pixel kernel includes two to four Z pixels. The RGB and Z pixels can be integrated together on a single sensor array.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: May 5, 2020
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Francois Roy
  • Patent number: 10634715
    Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 28, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Chittoor Parthasarathy
  • Publication number: 20200128204
    Abstract: A pixel of an imager device includes a photosensitive area configured to integrate a light signal. A first capacitive storage node is configured to receive a signal representative of the number of charges generated by the photosensitive area. A second capacitive storage node is configured to receive a reference signal. A first transfer transistor is coupled between the first capacitive storage node and the photosensitive area. A second transfer transistor is coupled between the second capacitive storage node and a terminal which supplied the reference signal. The first and second two transfer transistors have a common conduction electrode and a common substrate, wherein the common substrate is coupled to the first capacitive storage node.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 23, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Pierre MALINGE