Patents Assigned to STMicroelectronics Crolles 2 SAS
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Patent number: 11908809Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.Type: GrantFiled: May 20, 2021Date of Patent: February 20, 2024Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SASInventors: Eric Sabouret, Krysten Rochereau, Olivier Hinsinger, Flore Persin-Crelerot
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Publication number: 20240053202Abstract: The present description concerns a polarimetric image sensor formed inside and on top of a semiconductor substrate, the second comprising a plurality of pixels, each comprising: —a photosensitive region formed in the semiconductor substrate; —a diffraction structure formed on the side of an illumination surface of the photosensitive region; and —a polarization structure formed on the side of the diffraction structure opposite to the photosensitive region.Type: ApplicationFiled: March 17, 2023Publication date: February 15, 2024Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SASInventors: Jerome VAILLANT, Francois DENEUVILLE, Axel CROCHERIE, Alain OSTROVSKY
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Patent number: 11901216Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.Type: GrantFiled: October 7, 2021Date of Patent: February 13, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Gouraud, Delia Ristoiu
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Patent number: 11901278Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.Type: GrantFiled: January 11, 2023Date of Patent: February 13, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Jean-Pierre Carrere, Francois Guyader
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Patent number: 11901381Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.Type: GrantFiled: July 9, 2020Date of Patent: February 13, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Andrej Suler
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Patent number: 11894382Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.Type: GrantFiled: December 7, 2021Date of Patent: February 6, 2024Assignees: STMicroelectronics France, STMicroelectronics (Crolles 2) SASInventors: Olivier Weber, Christophe Lecocq
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Patent number: 11895417Abstract: The present description describes an image sensor including an array of pixels arranged inside and on top of a region of a semiconductor substrate electrically insulated from the rest of the substrate by insulating trenches crossing the substrate, each pixel including a photoconversion area and at least two assemblies, each including a memory area and a transfer gate coupling the memory area to the photoconversion area, and a circuit configured to apply, for each pixel and at least during each integration phase, a bias voltage different from ground to a portion of the substrate having the pixel arranged inside and on top of it.Type: GrantFiled: February 8, 2022Date of Patent: February 6, 2024Assignees: STMicroelectronics France, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Crolles 2) SASInventors: Celine Mas, Matteo Maria Vignetti, Francois Agut
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Publication number: 20240030255Abstract: The present disclosure relates to an image sensor including a plurality of pixels formed in and on a semiconductor substrate and arranged in a matrix with N rows and M columns, with N being an integer greater than or equal to 1 and M an integer greater than or equal to 2. A plurality of microlenses face the substrate, and each of the microlenses is associated with a respective pixel. The microlenses are arranged in a matrix in N rows and M columns, and the pitch of the microlens matrix is greater than the pitch of the pixel matrix in a direction of the rows of the pixel matrix.Type: ApplicationFiled: August 2, 2023Publication date: January 25, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Lucie DILHAN, Jerome VAILLANT
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Publication number: 20240023465Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.Type: ApplicationFiled: March 17, 2023Publication date: January 18, 2024Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA, STMicroelectronics (Crolles 2) SASInventors: Bruno REIG, Vincent PUYAL, Stephane MONFRAY, Alain FLEURY, Philippe CATHELIN
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Publication number: 20240023468Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.Type: ApplicationFiled: March 27, 2023Publication date: January 18, 2024Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS SAInventors: Alain FLEURY, Stephane MONFRAY, Philippe CATHELIN, Bruno REIG, Vincent PUYAL
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Publication number: 20240023467Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.Type: ApplicationFiled: March 17, 2023Publication date: January 18, 2024Applicants: STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Stephane MONFRAY, Alain FLEURY, Bruno REIG
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Publication number: 20240014342Abstract: A device includes a single photon avalanche diode in a substrate and a resistor. The resistor is provided resting on an insulating trench located in a doped anode region of the single photon avalanche diode.Type: ApplicationFiled: July 10, 2023Publication date: January 11, 2024Applicants: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Crolles 2) SASInventors: Sara PELLEGRINI, Dominique GOLANSKI, Alexandre LOPEZ
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Publication number: 20240014341Abstract: A device includes a single photon avalanche diode in a portion of a substrate, wherein the portion has an octagonal profile. The octagonal profile is delimited by a wall forming an octagonal contour around the portion. The device further includes an array of diodes, wherein each diode is located in a corner between four adjacent single photon avalanche diodes. Each single photon avalanche diode further includes a doped anode region. A shallow trench isolation is formed in each doped anode region. A polysilicon line forming a resistor is supported at the upper surface of the shallow trench isolation.Type: ApplicationFiled: July 10, 2023Publication date: January 11, 2024Applicants: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Crolles 2) SASInventors: Isobel NICHOLSON, Sara PELLEGRINI, Dominique GOLANSKI, Alexandre LOPEZ
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Patent number: 11869772Abstract: A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.Type: GrantFiled: June 3, 2021Date of Patent: January 9, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Denis Monnier, Olivier Gonnard
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Publication number: 20230420472Abstract: An image sensor is includes a plurality of pixels. Each of the pixels includes a silicon photoconversion region and a material that at least partially surrounds the photoconversion region. The material has a refraction index smaller than the refraction index of silicon, and the interface between the photoconversion region of the pixel and the material is configured so that at least one ray reaching the photoconversion region of the pixel undergoes a total reflection or a plurality of successive total reflections at the interface.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Applicant: STMicroelectronics (Crolles 2) SASInventor: Axel CROCHERIE
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Publication number: 20230411450Abstract: The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.Type: ApplicationFiled: June 6, 2023Publication date: December 21, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Remy BERTHELON, Olivier WEBER
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Publication number: 20230408738Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.Type: ApplicationFiled: July 28, 2023Publication date: December 21, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Vincent FARYS, Alain INARD, Olivier NOBLANC
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Patent number: 11843008Abstract: An electronic device includes a stack of a first level having a SPAD, a second level having a quench circuit for said SPAD, and a third level having a circuit for processing data generated by said SPAD. A method for making the device includes: a) forming of the first level; b) bonding, on the first level, by molecular bonding, of a stack of layers including a semiconductor layer; and c) forming the quench circuit of the second level in the semiconductor layer.Type: GrantFiled: October 11, 2021Date of Patent: December 12, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Research & Development) LimitedInventors: Francois Guyader, Sara Pellegrini, Bruce Rae
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Patent number: 11837647Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.Type: GrantFiled: March 3, 2022Date of Patent: December 5, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Alexis Gauthier, Pascal Chevalier
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Patent number: 11837678Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.Type: GrantFiled: September 27, 2021Date of Patent: December 5, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Charles Baudot, Sebastien Cremer, Nathalie Vulliet, Denis Pellissier-Tanon
