Patents Assigned to STMicroelectronics Crolles 2 SAS
  • Publication number: 20200119269
    Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Pierre MORIN, Michel HAOND, Paola ZULIANI
  • Patent number: 10622460
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Guillaume C. Ribes
  • Publication number: 20200111889
    Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER
  • Publication number: 20200111890
    Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER
  • Patent number: 10613202
    Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 7, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Boris Rodrigues Goncalves, Marie Guillon, Yvon Cazaux, Benoit Giffard
  • Publication number: 20200081476
    Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Guenole LALLEMENT, Fady ABOUZEID
  • Patent number: 10587131
    Abstract: The invention concerns a measurement unit including: an electric ambient energy recovery generator; an element of capacitive storage of the electric energy generated by the generator; an electric battery; a first branch coupling an output node of the generator to a first electrode of the capacitive storage element; a second branch coupling a first terminal of the battery to the first electrode of the capacitive storage element; and an active circuit capable of transmitting a radio event indicator signal each time the voltage across the capacitive storage element exceeds a first threshold, wherein, in operation, the capacitive storage element simultaneously receives a first charge current originating from the generator via the first branch and a second charge current originating from the battery via the second branch.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 10, 2020
    Assignees: Commissariat à I'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Séverin Trochut, Stéphane Monfray, Sébastien Boisseau
  • Patent number: 10585143
    Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 10, 2020
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pascal Urard, Florian Cacho, Vincent Huard, Alok Kumar Tripathi
  • Patent number: 10566376
    Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 18, 2020
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Roy, Frédéric Lalanne, Pierre Emmanuel Marie Malinge
  • Patent number: 10559611
    Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: February 11, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Philippe Are
  • Patent number: 10546929
    Abstract: An integrated circuit includes a substrate; a buried insulating layer; at least one nMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one pMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one semiconductor groundplane that may be doped or a metal, placed above the substrate and below the buried insulating layer, said buried plane being common to the nMOS transistor and to the pMOS transistor; at least one gate insulator and a gate that is common to the nMOS transistor and to the pMOS transistor and that is located above the channel of these transistors and facing the groundplane, the area of the groundplane at least covering the area of the gate in vertical projection; the nMOS transistor being separated from the pMOS transistor by an isolation defined between the semiconductor layer of the nMOS transistor and the semiconductor layer of the pMOS transistor, the isolation being located in the buried insulating l
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 28, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: François Andrieu, Remy Berthelon
  • Publication number: 20200020589
    Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Loic GABEN
  • Patent number: 10532379
    Abstract: A mechanical structure comprising a stack including an active substrate and at least one actuator designed to generate vibrations at the active substrate, the stack comprises an elementary structure for amplifying the vibrations: positioned between the actuator and the active substrate, the structure designed to transmit and amplify the vibrations; and comprising at least one trench, located between the actuator and the active substrate. A method for manufacturing the structure comprising the use of a temporary substrate is provided.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 14, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS, UNIVERSITÉ GRENOBLE ALPES
    Inventors: Fabrice Casset, Skandar Basrour, Cédrick Chappaz, Jean-Sébastien Danel
  • Patent number: 10535693
    Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Publication number: 20200013856
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER
  • Patent number: 10531022
    Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: January 7, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 10522593
    Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 31, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Emmanuel Gourvest, Yannick Le Friec, Laurent Favennec
  • Publication number: 20190393207
    Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre AYRES, Bertrand BOROT
  • Patent number: 10514749
    Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: December 24, 2019
    Assignees: STMicroelectonics (Crolles 2) SAS, STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Silvia Brini, Chittoor Parthasarathy
  • Publication number: 20190386142
    Abstract: A ferroelectric field effect transistor includes a semiconductor substrate, with first and second source/drain regions being formed within the semiconductor substrate and being separated by a channel region. An interface layer is disposed on the channel region. A gate insulator layer is disposed on the interface layer. A ferroelectric layer is disposed on the gate insulator layer.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 19, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael GROS-JEAN, Julien FERRAND