Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

Abstract: A method includes receiving a plurality of digital feedback signals from a voltage converter, controlling the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, the voltage converter receiving input from a DC voltage bus and providing output to drive a lighting load, and receiving a plurality of feedback signals from a power factor correction circuit that receives a rectified mains voltage and provides output to the DC voltage bus, and based thereupon operating the power factor correction circuit in transition mode or discontinuous mode based upon the user desired brightness level and a threshold brightness. The plurality of feedback signals include an input sense signal that is a function of the rectified mains voltage as drawn by the power factor correction circuit and an output sense signal that is a function of the output provided to the DC voltage bus.

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

Abstract: ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.

Abstract: A thyristor is formed from a vertical stack of first, second, third, and fourth semiconductor regions of alternated conductivity types. The fourth semiconductor region is interrupted in a gate area of the thyristor. The fourth semiconductor region is further interrupted in a continuous corridor that extends longitudinally from the gate area towards an outer lateral edge of the fourth semiconductor region. A gate metal layer extends over the gate area of the thyristor. A cathode metal layer extends over the fourth semiconductor region but not over the continuous corridor.

Abstract: A system on chip (SoC) includes a system clock device configured to generate at least one system clock signal, a first area with a central processing unit and a second area with a direct memory access (DMA) circuit, a peripheral coupled to the DMA circuit, and a memory containing peripheral configuration descriptor(s) executable by the DMA circuit. In a first mode of SoC operation, the system clock device delivers the system clock signal to all areas. In a second mode of SoC operation, the system clock device does not deliver the system clock signal to any area. In a third mode of SoC operation, the system clock device distributes the system clock signal to a part of the second area without delivering the system clock signal to the other areas and the DMA circuit configures the peripheral in response to the execution of the configuration descriptor(s).

Abstract: A pixel includes a first electrode layer on an exposed surface of an interconnection structure and in contact with a conductive element of the interconnection structure. An insulating layer extends over the first electrode layer and includes opening crossing through the insulating layer to the first electrode layer. A second electrode layer is on top of and in contact with the first electrode layer and the insulating layer in the opening. A film configured to convert photons into electron-hole pairs is on the insulating layer, the second electrode layer and filling the opening. A third electrode layer covers the film.

Abstract: A PLL circuit includes a fractional-N divider generating a feedback signal, a first phase-frequency detector that compares the feedback signal to a reference signal to generate first up/down control signals that control a charge pump to generate a charge pump output current. A noise cancelation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase-frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up/down control signals whose pulse widths differ by the integer number of PLL cycles. A current digital to analog converter circuit is controlled in response to the second up/down control signals to apply noise canceling sourcing and sinking currents to the charge pump output current.

Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

Abstract: An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.

Abstract: A first object and a second object are movable in relation to one another. The first object includes a transponder using an integrated circuit having two terminals which may or may not be shorted. The presence or absence of a short circuit between the two terminals is detected. This is accomplished at least partly by the second object depending on the relative positioning of the first and second objects. The transponder transmits, to a module having a contactless reader function, positioning information corresponding to said relative positioning using a contactless communication protocol.

Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.

Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

Abstract: An electronic chip includes an analog input connection pad and an analog output connection pad. A switch is coupled between the analog input connection pad and the analog output connection pad. In one embodiment, the chip operates in a self-test mode and in an active mode. The switch is closed only in the self-test mode.

Abstract: An electronic device includes a test voltage generation circuit to generate a test voltage as a function of a regulator voltage, and a switching circuit to receive the test voltage and an image pixel output signal, and to pass the test voltage as output when in a test mode. A comparison circuit receives the output from the switching circuit and an analog to digital conversion signal, and asserts a counter reset signal when the output from the switching circuit and the analog to digital conversion signal are equal in voltage. A counter begins counting at a beginning of each test cycle within the test mode, stops counting upon assertion of the counter rest signal, and outputs its count upon stopping counting. The count is proportional to the test voltage when in the test mode.

Abstract: A first independent unit includes a support substrate with an integrated network of electrical connections. An electronic integrated circuit chip is mounted above a front face of the support substrate. A second independent unit includes a dielectric support. The second independent unit is stacked above the first independent unit on a side of the front face of the first independent unit. An electromagnetic antenna includes an exciter element and a resonator element. The exciter element provided at the support substrate. The resonator element is provided at the dielectric support.

Abstract: An electronic integrated circuit (IC) component is mounted to a substrate. A cap member is applied onto the substrate and covers the electronic IC component. The cap member includes an outer wall defining an opening and an inner wall surrounding the electronic IC component. The inner wall extends from a proximal end at the substrate towards a distal end facing the opening in the outer wall to provide a reception chamber for the electronic IC component and a peripheral chamber between the inner wall and the outer wall of the cap member. An encapsulant material is provided in the reception chamber to seal the electronic IC component without being present in the peripheral chamber.

Abstract: Embodiments are directed to electrically confined ballistic devices, circuits, and networks. One such device includes a heterostructure that has a first semiconductor layer, a second semiconductor layer, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. The device further includes an input electrode electrically coupled to the 2DEG layer and an output electrode electrically coupled to the 2DEG layer. A first confinement electrode is positioned on the heterostructure. The first confinement electrode, in use, generates first space charge regions which at least partially define a boundary of the ballistic device within the 2DEG layer between the input electrode and the output electrode in response to a first voltage.

Abstract: A microelectromechanical mirror device has a fixed structure defining a cavity. A tiltable structure carrying a reflecting surface is elastically suspended above the cavity with a main extension in a horizontal plane. Elastic elements are coupled to the tiltable structure and at least one first pair of driving arms, which carry respective regions of piezoelectric material, are biasable to cause rotation of the tiltable structure about at least one first axis of rotation parallel to a first horizontal axis of the horizontal plane. The driving arms are elastically coupled to the tiltable structure on opposite sides of the first axis of rotation and are interposed between the tiltable structure and the fixed structure. The driving arms have a thickness, along an orthogonal axis transverse to the horizontal plane, smaller than a thickness of at least some of the elastic elements coupled to the tiltable structure.