Abstract: A device operate by alternating between first and second phases of operation. The device includes a first transistor and a first circuit. The first circuit operates to: couple a first conduction terminal of the first transistor to an output node of the device and a second conduction terminal of the first transistor to a first node of application of a potential during each first phase; and couple the first terminal of the first transistor to a second node of application of a potential and the second conduction terminal of the first transistor to the output node during each second phase of operation.
Abstract: A system includes a random number generator generating a random number in response to an event. Control logic generates hierarchical part alignment selectors from the random number. For each secure data block to be stored in volatile storage, a physical address of a first logical address for that secure data block is set based upon the hierarchical part alignment selectors. For each data word within that secure data block, a physical address of a first logical address for that data word is set based upon the hierarchical part alignment selectors. For each data byte within that data word, a physical address of a first logical address for that data byte is set based upon the hierarchical part alignment selectors. A physical address of a logical address for a first data bit within that data byte is set based upon the hierarchical part alignment selectors.
Abstract: A system includes inertial sensors and a GPS. The system generates a first estimated vehicle velocity based on motion data and positioning data, generates a second estimated vehicle velocity based on the processed motion data and the first estimated vehicle velocity, and generates fused datasets indicative of position, velocity and attitude of a vehicle based on the processed motion data, the positioning data and the second estimated vehicle velocity. The generating the second estimated vehicle velocity includes: filtering the motion data, transforming the filtered motion data in a frequency domain based on the first estimated vehicle velocity, generating spectral power density signals, generating an estimated wheel angular frequency and an estimated wheel size based on the spectral power density signals, and generating the second estimated vehicle velocity as a function of the estimated wheel angular frequency and the estimated wheel size.
Type:
Application
Filed:
September 9, 2021
Publication date:
March 17, 2022
Applicants:
STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC., STMicroelectronics (Grand Ouest) SAS
Inventors:
Nicola Matteo PALELLA, Leonardo COLOMBO, Andrea DONADEL, Roberto MURA, Mahaveer JAIN, Joƫlle PHILIPPE
Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.
Type:
Application
Filed:
September 9, 2021
Publication date:
March 17, 2022
Applicants:
STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SAS
Inventors:
Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
Abstract: In at least one embodiment, a Geiger-mode avalanche photodiode, including a semiconductor body, is provided. The semiconductor body includes a semiconductive structure and a front epitaxial layer on the semiconductive structure. The front epitaxial layer has a first conductivity type. An anode region having a second conductivity type that is different from the first conductivity type extends into the front epitaxial layer. The photodiode further includes a plurality of gettering regions in the semiconductive structure.
Abstract: An optical filter includes a carrier layer made of a first material. A periodic grating of posts is disposed on the carrier layer in a periodic pattern configured by characteristic dimensions. The posts are made of a second material. A layer made of a third material encompasses the periodic grating of posts and covers the carrier layer. The third material has a refractive index that is different from a refractive index of the second material. Characteristic dimensions of the periodic grating of posts are smaller than an interfering wavelength and are configured to selectively reflect light at the interfering wavelength on the periodic grating of posts.
Type:
Application
Filed:
September 8, 2021
Publication date:
March 17, 2022
Applicants:
STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
Inventors:
Olivier LE NEEL, Stephane ZOLL, Stephane MONFRAY
Abstract: A photosensitive semiconductor region is configured to be illuminated through a rear face. A periodic array of pads formed of a first material is provided at the front face. The periodic array has an outline with a periodic pattern parameterized by characteristic dimensions. The outline forms an interface between the first material and a second material, where the first and second materials have different optical indices. The characteristic dimensions of the periodic pattern are less than a wavelength of interest and are configured to produce at the interface a reflection of light at the wavelength of interest towards the photosensitive semiconductor region.
Abstract: A microelectromechanical device includes: a body accommodating a microelectromechanical structure; and a cap bonded to the body and electrically coupled to the microelectromechanical structure through conductive bonding regions. The cap including a selection module, which has first selection terminals coupled to the microelectromechanical structure, second selection terminals, and at least one control terminal, and which can be controlled through the control terminal to couple the second selection terminals to respective first selection terminals according, selectively, to one of a plurality of coupling configurations corresponding to respective operating conditions.
Type:
Grant
Filed:
March 11, 2020
Date of Patent:
March 15, 2022
Assignee:
STMicroelectronics S.r.l.
Inventors:
Giorgio Allegato, Barbara Simoni, Carlo Valzasina, Lorenzo Corso
Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.
Abstract: An amplification interface includes an input terminal receiving a sensor current and an output terminal supplying an output voltage. An analog integrator is connected to the input terminal and supplies the output voltage. A current generator is connected to the input of the analog integrator and generates a compensation current based on a drive signal. A control circuit generates the drive signal for the current generator based on a control signal representing an offset in the sensor current supplied by the sensor. The current generator generates, based on the driving signal, a positive or negative current. The control circuit determines a first duration and a second duration as a function of the control signal representing the offset in the sensor current, during the measurement interval, and sets the driving signal to a first logic value for the first duration and to a second logic value for the second duration.
Type:
Grant
Filed:
February 4, 2020
Date of Patent:
March 15, 2022
Assignee:
STMicroelectronics S.r.l.
Inventors:
Michele Vaiana, Calogero Marco Ippolito, Angelo Recchia, Antonio Cicero, Pierpaolo Lombardo
Abstract: In an embodiment of the present invention, a method for controlling a voltage across a single photon avalanche diode includes: providing an output based on a current flowing through the single photon avalanche diode; and controlling the voltage applied across the single photon avalanche diode based on the provided output.
Abstract: A first wafer of semiconductor material has a surface. A second wafer of semiconductor material includes a substrate and a structural layer on the substrate. The structural layer integrates a detector device for detecting electromagnetic radiation. The structural layer of the second wafer is coupled to the surface of the first wafer. The substrate of the second wafer is shaped to form a stator, a rotor, and a mobile mass of a micromirror. The stator and the rotor form an assembly for capacitively driving the mobile mass.
Type:
Grant
Filed:
January 16, 2020
Date of Patent:
March 15, 2022
Assignee:
STMicroelectronics S.r.l.
Inventors:
Luca Seghizzi, Linda Montagna, Giuseppe Visalli, Mikel Azpeitia Urquia
Abstract: Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.
Abstract: A processor interacts with a memory set including a cache memory, a first memory storing at least a first piece of information in a first information group, and a second memory storing at least a second piece of information in a second information group. In response to a first cache miss and following a first request from the processor for the first piece of information, the first piece of information obtained from the first memory is supplied to the processor. After a second request from the processor for the second piece of information, the second piece of information obtained from the second memory is supplied to the processor, even if the first information group is currently being transferred from the first memory for loading into the cache memory.
Type:
Grant
Filed:
September 17, 2019
Date of Patent:
March 15, 2022
Assignees:
STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
Abstract: A power transistor and a cascode transistor are connected in series. A driver circuit has an output driving a control terminal of the power transistor. The driver circuit has a first power supply node coupled to receive a floating voltage that is also applied to a control terminal of the cascode transistor. A variable voltage generator generates the floating voltage. The floating voltage track either a power supply voltage or a reference voltage over a first range of voltage levels for the power supply voltage. The floating voltage further satisfies a ratio metric relationship dependent on the power supply voltage and reference voltage over a second range of voltage levels for said power supply voltage.
Abstract: A microcircuit card is provided with a fingerprint sensor. Customization of the microcircuit card is accomplished by the use of an exchange of data by near-field communications between the microcircuit card and a near-field communication device. A mechanical positioning system associated with the near-field communication device is configured to retain the microcircuit card such that the fingerprint sensor is accessible and near-field communication between the microcircuit card and the near-field communication device is assured. The mechanical positioning system may, in an example where the near-field communication device is a cell phone, be formed by a slot of a protective case for the cell phone.
Abstract: A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.
Abstract: A semiconductor substrate of an integrated circuit is protected by a coating. The semiconductor includes a front face and a rear face. To detect a breach of the integrity of a semiconductor substrate of an integrated circuit from the rear face, an opening of the coating facing the rear face of the substrate is detected. In response thereto, an alarm is generated. The detection is performed by making resistance measurements with respect to the semiconductor substrate and comparing the measured resistance to a nominal resistive value of the semiconductor substrate.
Type:
Grant
Filed:
February 5, 2019
Date of Patent:
March 8, 2022
Assignee:
STMicroelectronics (Rousset) SAS
Inventors:
Alexandre Sarafianos, Bruno Nicolas, Daniele Fronte
Abstract: In an embodiment, a circuit for tripling frequency is configured to receive an input voltage (Vin) having a sinusoidal shape and a base frequency. The circuit has a first and a second transistor pair that are cross-coupled, and a trans-characteristics f(Vin) approximating a polynomial nominal trans-characteristic given by f ? ( V in ) = ( 3 A ? V in - 4 A 3 ? V in 3 ) ? g m where A represents an amplitude of the input voltage and gm is a transconductance of transistors of the first and second transistor pairs.
Type:
Grant
Filed:
September 18, 2020
Date of Patent:
March 8, 2022
Assignee:
STMicroelectronics S.r.l.
Inventors:
Mahmoud Mahdipour Pirbazari, Andrea Mazzanti, Andrea Pallotta
Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.