Patents Assigned to STMicroelectronics (Crolles 2)
  • MEMS GYROSCOPE SELF-TEST USING A TECHNIQUE FOR DEFLECTION OF THE SENSING MOBILE MASS
    Publication number: 20220128360
    Abstract: A microelectromechanical system (MEMS) gyroscope sensor has a sensing mass and a quadrature error compensation control loop for applying a force to the sensing mass to cancel quadrature error. To detect fault, the quadrature error compensation control loop is opened and an additional force is applied to produce a physical displacement of the sensing mass. A quadrature error resulting from the physical displacement of the sensing mass in response to the applied additional force is sensed. The sensed quadrature error is compared to an expected value corresponding to the applied additional force and a fault alert is generated if the comparison is not satisfied.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Yamu HU, Deyou FANG, David MCCLURE, Huantong ZHANG, Naren K. SAHOO
  • METHOD OF OPERATING ELECTRO-ACOUSTIC TRANSDUCERS, CORRESPONDING CIRCUIT AND DEVICE
    Publication number: 20220128674
    Abstract: A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marco PASSONI, Niccolò PETRINI
  • METHOD FOR PRODUCING A DIODE
    Publication number: 20220130728
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
  • NORMALLY-OFF TRANSISTOR WITH REDUCED ON-STATE RESISTANCE AND MANUFACTURING METHOD
    Publication number: 20220130990
    Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ferdinando IUCOLANO, Alfonso PATTI
  • SEMICONDUCTOR INTEGRATED CIRCUIT COMPONENT
    Publication number: 20220131005
    Abstract: An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region.
    Type: Application
    Filed: October 19, 2021
    Publication date: April 28, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Benoit FROMENT, Thomas CABOUT
  • Method for the generation of personalized profile package data in integrated circuit cards
    Patent number: 11314852
    Abstract: A method can be used for the generation of personalized Profile Package data in integrate circuit cards. A table includes data records corresponding to subscriptions to be generated. Each record includes personalization fields to store different types of personalization values. For a given subscription, a file for the Profile Package is in an ASCII format and includes fields to be personalized corresponding to one or more of the fields to store different types of personalization values. The file for the Profile Package in the ASCII format is converted into a hexadecimal code. An offset table is calculated for the given subscription indicating for each field to be personalized a corresponding offset in the hexadecimal profile. The personalization values from the personalization fields are substituted in the corresponding personalization fields to be personalized.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 26, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Alfarano, Giancarlo Pasquariello
  • Method of operating battery management systems, corresponding device and vehicle
    Patent number: 11312238
    Abstract: A method can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A faulty condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is swapped for a first swapped voltage drop between a common terminal and the second terminal of the second battery cell.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 26, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Orazio Pennisi, Valerio Bendotti, Vittorio D'Angelo, Paolo Turbanti
  • DEVICE AND METHOD FOR READING DATA FROM MEMORY CELLS
    Publication number: 20220122657
    Abstract: An integrated circuit includes a memory array. The memory array includes a plurality of bitlines. The bitlines are each coupled to a respective local I/O circuit. All of the local I/O circuits are coupled to a global I/O circuit. Each local I/O circuit includes a first sensing stage for reading data from the memory cell. The global I/O circuit includes a second sensing stage for reading data from the memory cell.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics International N.V.
    Inventor: Kedar Janardan DHORI
  • PIEZOELECTRIC MICROMACHINED ULTRASONIC TRANSDUCER
    Publication number: 20220118480
    Abstract: A PMUT device includes a membrane element extending perpendicularly to a first direction and configured to generate and receive ultrasonic waves by oscillating about an equilibrium position. At least two piezoelectric elements are included, with each one located over the membrane element along the first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. The membrane element has a lobed shape along a plane perpendicular to the first direction, with the lobed shape including at least two lobes. The membrane element includes for each piezoelectric member a corresponding membrane portion including a corresponding lobe, with each piezoelectric member being located over its corresponding membrane portion.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico GIUSTI, Fabio QUAGLIA, Marco FERRERA
  • ARTIFICIAL NEURON
    Publication number: 20220121913
    Abstract: An artificial neuron includes a first capacitive node of application of a membrane potential of the neuron. A first transistor is configured to discharge the first capacitive node. A second capacitive node is driven according to the membrane potential and delivers a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitive node. The second transistor is controlled according to a potential present at the second capacitive node.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics SA
    Inventors: Valerian CINCON, Philippe GALY
  • NON-VOLATILE MEMORY
    Publication number: 20220123119
    Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Philippe BOIVIN, Francois TAILLIET, Roberto SIMOLA
  • MOS TRANSISTOR ISOLATED FROM THE SUBSTRATE OF AN INTEGRATED CIRCUIT AND APPLICATION FOR DETECTING AN OPENING OF A CLOSED CONTAINER
    Publication number: 20220120589
    Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal FORNARA
  • SQUELCH DETECTION DEVICE
    Publication number: 20220123699
    Abstract: A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to produce an average common mode and sets the first common mode of the first and second input signals to the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages to the average common mode and determines a state of a squelch signal, indicative of whether the first and second input signals are attributable to noise, based on the first and second input signals and the first and second threshold voltages.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics International N.V.
    Inventor: Prashant Singh
  • METHOD FOR MANUFACTURING A WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
    Publication number: 20220122941
    Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.
    Type: Application
    Filed: September 23, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics PTE LTD
    Inventors: Chun Yi TENG, David GANI
  • PIEZOELECTRIC MICROMACHINED ULTRASONIC TRANSDUCER HAVING REDUCED FREE OSCILLATIONS
    Publication number: 20220119246
    Abstract: A PMUT device includes a membrane element adapted to generate and receive ultrasonic waves by oscillating, about an equilibrium position, at a corresponding resonance frequency. A piezoelectric element is located over the membrane element along a first direction and configured to cause the membrane element to oscillate when electric signals are applied to the piezoelectric element, and generate electric signals in response to oscillations of the membrane element. A damper is configured to reduce free oscillations of the membrane element, and the damper includes a damper cavity surrounding the membrane element, and a polymeric member having at least a portion over the damper cavity along the first direction.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Domenico GIUSTI, Marco FERRERA, Fabio QUAGLIA
  • ELECTRODE STRUCTURE HAVING IMPROVED SHAPE, AND ELECTRONIC DEVICE INCLUDING THE ELECTRODE STRUCTURE
    Publication number: 20220123105
    Abstract: An electrode structure includes a pad of conductive material, and a conductive strip having a first end physically and electrically coupled to the pad. The pad includes an annular element internally defining a through opening. The first end of the conductive strip is physically and electrically coupled to the annular element by a transition region so that, when the conductive strip undergoes expansion by the thermal effect, a stress spreads from the conductive strip to the annular element by the transition region.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Fabrizio CERINI, Silvia ADORNO, Dario PACI, Marco SALINA
  • BIPOLAR TRANSISTOR AND MANUFACTURING METHOD
    Publication number: 20220122969
    Abstract: A bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion covering and in contact with an area of the first doped portion. The collector region has a doping profile having a peak in the first portion and a decrease from this peak up to in the second portion.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Edoardo BREZZA, Alexis GAUTHIER
  • DISCHARGE OF AN AC CAPACITOR
    Publication number: 20220123650
    Abstract: A circuit includes two thyristors coupled in anti-series. An AC capacitor has first and second electrodes respectively coupled to two different electrodes of the two thyristors. The first and second electrodes are coupled to receive an AC voltage. A control circuit detects discontinuance of application of the AC voltage to the AC capacitor and in response thereto simultaneously applies same gate currents to the two thyristors. A current path through the two thyristors (one passing current in forward mode and the other in reverse mode) discharges a residual voltage stored on the AC capacitor.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 21, 2022
    Applicant: STMicroelectronics LTD
    Inventor: Laurent GONTHIER
  • MEMS DEVICE HAVING AN IMPROVED STRESS DISTRIBUTION AND MANUFACTURING PROCESS THEREOF
    Publication number: 20220119245
    Abstract: A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Nicolo' BONI, Lorenzo VINCIGUERRA, Roberto CARMINATI, Massimiliano MERLI
  • Open vs enclosed spatial environment classification for a mobile or wearable device using microphone and deep learning method
    Patent number: 11308979
    Abstract: A method and apparatus for classifying a spatial environment as open or enclosed are provided. In the method and apparatus, one or more microphones detect ambient sound in a spatial environment and output an audio signal representative of the ambient sound. A processor determines a spatial environment impulse response (SEIR) for the audio signal and extracts one or more features of the SEIR. The processor classifies the spatial environment as open or enclosed based on the one or more features of the SEIR.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: April 19, 2022
    Assignees: STMicroelectronics, Inc., STMicroelectronics International N.V.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Rajendar Bahl