Patents Assigned to STMicroelectronics (Crolles 2)
  • Publication number: 20220139899
    Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 5, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Roberto SIMOLA
  • Publication number: 20220137400
    Abstract: An optical package includes a beam combiner that combines laser light from a laser unit into a single laser beam, a movable mirror apparatus, and a fixed folding mirror which reflects the single laser beam toward the movable mirror apparatus. Beam equalizer optics cause increase of a slow axis divergence rate of the single laser beam such that its slow axis divergence rate is equal to its fast axis divergence rate. The movable mirror apparatus directs the single laser beam through an exit window. The beam equalizer optics include at least one negative spherical lens shaped such that a slow axis divergence rate of incident light is increased but a fast axis divergence rate of incident light is unaltered.
    Type: Application
    Filed: October 25, 2021
    Publication date: May 5, 2022
    Applicant: STMicroelectronics LTD
    Inventors: Alex DOMNITS, Shlomy ERLICH
  • Publication number: 20220137128
    Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicants: STMicroelectronics International N.V., STMicroelectronics Application GmbH, STMicroelectronics S.r.l.
    Inventors: Avneep Kumar GOYAL, Deepak BARANWAL, Thomas SZURMANT, Nicolas Bernard GROSSIER
  • Publication number: 20220138530
    Abstract: An artificial-neuron device includes an integration-generation circuit coupled between an input at which an input signal is received and an output at which an output signal is delivered, and a refractory circuit inhibiting the integrator circuit after the delivery of the output signal. The refractory circuit is formed by a first MOS transistor having a first conduction-terminal coupled to a supply node, a second conduction-terminal coupled to a common node, and a control-terminal coupled to the output, and a second MOS transistor having a first conduction-terminal coupled to the input, a second conduction-terminal coupled to a reference node at which a reference voltage is received, and a control-terminal coupled to the common node. A resistive-capacitive circuit is coupled between the supply node and the reference node and having a tap coupled to the common node, with the inhibition duration being dependent upon a time constant of the resistive-capacitive circuit.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Thomas BEDECARRATS
  • Publication number: 20220139782
    Abstract: An integrated circuit includes metal-oxide-semiconductor “MOS” transistors formed on a semiconductor substrate. The MOS transistors have gate stacks belonging to at least one gate stack category and dielectric regions of sidewall spacers on the sides of the gate stacks. At least a first MOS transistor has a gate stack of said at least one gate stack category that includes dielectric regions of sidewall spacers having a first width. At least a second MOS transistor has a gate stack of the same gate stack category with dielectric regions of sidewall spacers having a second width different from the first width.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 5, 2022
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Franck JULIEN
  • Publication number: 20220140232
    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
    Type: Application
    Filed: October 21, 2021
    Publication date: May 5, 2022
    Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Philippe BOIVIN, Roberto SIMOLA, Yohann MOUSTAPHA-RABAULT
  • Publication number: 20220140176
    Abstract: A method of making a light sensor module includes connecting a light sensing circuit to an interconnect on a substrate, and forming a cap. The cap is formed by producing a cap substrate from material opaque to light to have an opening formed therein, placing the cap substrate top-face down, dispensing a light transmissible material into the opening, compressing the light transmissible material using a hot tool to thereby cause the light transmissible material to fully flow into the opening to form at a light transmissible aperture, and placing the cap substrate into a curing environment. A bonding material is dispensed onto the substrate. The cap is picked up and placed onto the substrate positioned such that the light transmissible aperture is aligned with the light sensing circuit, with the bonding material bonding the cap to the substrate to thereby form the light sensor module.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Jaspreet Singh SIDHU, Tat Ming TEO
  • Publication number: 20220137133
    Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.
    Type: Application
    Filed: October 18, 2021
    Publication date: May 5, 2022
    Applicant: STMicroelectronics International N.V.
    Inventors: Rohit GOEL, Anand Kumar MISHRA, Rajnish GARG
  • Publication number: 20220140571
    Abstract: A compact optical package includes an RGB laser unit containing red, green, and blue laser diodes within a single package, with three lenses adjacent the RGB laser unit to collimate red, green, and blue laser light emitted by the red, green, and blue laser diodes. A beam combiner combines the red, green, and blue laser light into a single RGB laser beam and also outputs a lower power feedback beam. The compact optical package also includes a movable mirror apparatus, and a fixed folding mirror upon which the single RGB laser beam output by the beam splitter impinges and reflects the single RGB laser beam toward the movable mirror apparatus. The movable mirror apparatus directs the single RGB laser beam through an exit window and to scan the single RGB laser beam in a scan pattern to form at least one desired image on a target.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Applicant: STMicroelectronics Ltd
    Inventor: Alex DOMNITS
  • Publication number: 20220140657
    Abstract: A bridge rectifier is controlled by control circuitry to act a “regtifier” which both regulates and rectifies without the use of a traditional voltage regulator. To accomplish this, the gate voltages of transistors of the bridge that are on during a given phase may be modulated to dissipate excess power. Gate voltages of transistors of the bridge that are off during the given phase may alternatively or additionally be modulated to dissipate excess power. The regtifier may act as two half-bridges that each power a different voltage converter, with those voltage converters powering a battery. The voltage converters may be switched capacitor voltage converters that switch synchronously with switching of the two half-bridges as they perform rectification.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Yannick GUEDON
  • Publication number: 20220140744
    Abstract: A bridge rectifier and associated control circuitry collectively form a “regtifier” which rectifies an input time varying voltage and regulates the rectified output voltage produced without the use of a traditional voltage regulator. To accomplish this, the gate voltages of transistors of the bridge rectifier that are on during a given phase may be modulated via analog control (to increase the on-resistance of those transistors) or via pulse width modulation (to turn off those transistors prior to the end of the phase). The transistors of the bridge rectifier that would otherwise be off during a given phase may be turned on to help dissipate excess power and thereby regulate the output voltage. This modulation is based upon both a voltage feedback signal and a current feedback signal.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Yannick GUEDON
  • Patent number: 11323131
    Abstract: A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Gagan Midha, Kallol Chatterjee
  • Patent number: 11321270
    Abstract: A method for encoding a data value to be transmitted on an SPI serial bus includes an operation to modify a status register of a memory, at least at one chosen time instant, as a function of all or part of the data value to be transmitted.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Patent number: 11323031
    Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Cattani, Alessandro Gasparini
  • Patent number: 11322363
    Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Borrel, Magali Gregoire
  • Patent number: 11322503
    Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 11322666
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11320452
    Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal is applied to the sensing capacitor during a reset phase of a sensing circuit coupled to the sensing capacitor. The test signal is configured to cause an electrostatic force which produces a physical displacement of the mobile mass corresponding to a desired acceleration value. Then, during a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the physical displacement of the mobile mass is sensed. This sensed variation in capacitance is converted to a sensed acceleration value. A comparison of the sensed acceleration value to the desired acceleration value provides an indication of an error in operation of the MEMS accelerometer sensor if the sensed acceleration value and desired acceleration value are not substantially equal.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 3, 2022
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.r.l.
    Inventors: Yamu Hu, David McClure, Alessandro Tocchio, Naren K. Sahoo, Anthony Junior Casillan
  • Publication number: 20220128674
    Abstract: A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Marco PASSONI, Niccolò PETRINI
  • Publication number: 20220128360
    Abstract: A microelectromechanical system (MEMS) gyroscope sensor has a sensing mass and a quadrature error compensation control loop for applying a force to the sensing mass to cancel quadrature error. To detect fault, the quadrature error compensation control loop is opened and an additional force is applied to produce a physical displacement of the sensing mass. A quadrature error resulting from the physical displacement of the sensing mass in response to the applied additional force is sensed. The sensed quadrature error is compared to an expected value corresponding to the applied additional force and a fault alert is generated if the comparison is not satisfied.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Yamu HU, Deyou FANG, David MCCLURE, Huantong ZHANG, Naren K. SAHOO