Patents Assigned to STMicroelectronics (Crolles 2)
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Patent number: 11271570Abstract: The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.Type: GrantFiled: November 18, 2020Date of Patent: March 8, 2022Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SASInventors: Marc Gens, David Jacquet, Fabien Pousset, Elias El Haddad
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Patent number: 11271075Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.Type: GrantFiled: February 27, 2020Date of Patent: March 8, 2022Assignee: STMicroelectronics (Rousset) SASInventor: Abderrezak Marzaki
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Patent number: 11271393Abstract: A wireless-power-system includes a bridge-rectifier having first and second inputs coupled to first and second terminals of a coil, and an output coupled to a rectified voltage node. An excitation circuit is coupled to the first input. A protection circuit has a first connection node capacitively coupled to the first terminal. The protection circuit, in Q-factor measurement mode, clamps the first connection node when the first input is coupled to ground, and connects the first connection node to the rectified voltage node when the first input is coupled to a supply voltage. The protection circuit, in wireless power mode, is acting as one leg of the rectifier. A pass gate circuit is coupled between the first connection node and a sense node, and a sensing circuit is coupled to the sense node and measures a Q-factor of the wireless power system when the protection circuit is in Q-factor measurement mode.Type: GrantFiled: August 31, 2020Date of Patent: March 8, 2022Assignee: STMicroelectronics Asia Pacific Pte LtdInventors: Supriya Raveendra Hegde, Yannick Guedon, Huiqiao He
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Patent number: 11271478Abstract: A charge pump generates an output voltage. A first circuit generates a pulse width-modulated signal as a function of a deviation between the output voltage and a setpoint voltage. A second circuit receives a periodic signal and conditions the supply of the periodic signal to a control input of the charge pump as a function of the state of the pulse width-modulated signal.Type: GrantFiled: November 16, 2020Date of Patent: March 8, 2022Assignee: STMicroelectronics (Grenoble 2) SASInventor: Xavier Branca
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Patent number: 11270668Abstract: A method for detecting an orientation of a screen of a device includes having a two-dimensional (2D) detector array affixed to the device in a fixed orientation relative to the screen, where the 2D detector array includes a sensing area with a plurality of pixels; imaging a scene including a user in a foreground and a background onto the 2D detector array; extracting an information of the scene for each of the plurality of pixels of the sensing area, the information being extracted from the 2D detector array by an image sensor; identifying an asymmetry in a pixelated image of the scene that includes the information of the scene for each of the plurality of pixels of the sensing area; and based on the asymmetry in the image of the scene, determining the orientation of the screen relative to the user.Type: GrantFiled: November 30, 2020Date of Patent: March 8, 2022Assignee: STMicroelectronics (Research & Development) LimitedInventors: Jeffrey M. Raynor, Marek Munko
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Patent number: 11271493Abstract: A rectifying bridge has a thyristor coupled in series with a rectifying element between a first rectified output terminal of a rectifying bridge circuit and a second rectified output terminal of the rectifying bridge circuit. A diode is coupled in series with a DC voltage source between a gate of the thyristor and the second rectified output terminal.Type: GrantFiled: June 10, 2020Date of Patent: March 8, 2022Assignee: STMicroelectronics LTDInventors: Laurent Gonthier, Yu Tsao Lin
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Patent number: 11269986Abstract: A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.Type: GrantFiled: October 22, 2019Date of Patent: March 8, 2022Assignees: STMicroelectronics (Grand Ouest) SAS, STMicroelectronics (Rousset) SASInventors: Vincent Berthelot, Layachi Daineche
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Patent number: 11271561Abstract: A thyristor or triac control circuit includes a first capacitive element that is series-connected with a first diode between a first terminal and a second terminal intended to be coupled to a gate of the thyristor or triac. A second capacitive element is coupled between the second terminal and a third terminal intended to be connected to a conduction terminal of the thyristor or triac on the gate side of the thyristor or triac. A second diode is coupled between the third terminal and a node of connection of the first capacitive element and first diode.Type: GrantFiled: May 20, 2020Date of Patent: March 8, 2022Assignee: STMicroelectronics (Tours) SASInventors: Ghafour Benabdelaziz, Cedric Reymond
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Patent number: 11269051Abstract: A circuit includes an input port receiving an input signal having a first frequency. A phase-shifter network is coupled to the input port, receives the input signal, and produces therefrom first and second signals in quadrature with one another. Frequency multiplier circuitry has a common node and includes a first rectifier for rectifying the first signal to produce a first rectified signal having a second frequency that is twice the first frequency and to be applied to the common node, and a second rectifier rectifying the second signal to produce a second rectified signal having the second frequency and to be applied to the common node. A combination of the first and second rectified signals is available at the common node and includes harmonic contents at a frequency that is fourfold the first frequency.Type: GrantFiled: December 9, 2019Date of Patent: March 8, 2022Assignee: STMicroelectronics S.r.l.Inventor: Francesco Belfiore
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Publication number: 20220069430Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.Type: ApplicationFiled: August 23, 2021Publication date: March 3, 2022Applicant: STMicroelectronics (Alps) SASInventor: Deborah COGONI
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Publication number: 20220069570Abstract: A wireless-power-system includes a bridge-rectifier having first and second inputs coupled to first and second terminals of a coil, and an output coupled to a rectified voltage node. An excitation circuit is coupled to the first input. A protection circuit has a first connection node capacitively coupled to the first terminal. The protection circuit, in Q-factor measurement mode, clamps the first connection node when the first input is coupled to ground, and connects the first connection node to the rectified voltage node when the first input is coupled to a supply voltage. The protection circuit, in wireless power mode, is acting as one leg of the rectifier. A pass gate circuit is coupled between the first connection node and a sense node, and a sensing circuit is coupled to the sense node and measures a Q-factor of the wireless power system when the protection circuit is in Q-factor measurement mode.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Applicant: STMicroelectronics Asia Pacific Pte LtdInventors: Supriya Raveendra HEGDE, Yannick GUEDON, Huiqiao HE
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Publication number: 20220068395Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.Type: ApplicationFiled: August 20, 2021Publication date: March 3, 2022Applicant: STMicroelectronics S.r.l.Inventors: Marcella CARISSIMI, Fabio Enrico Carlo DISEGNI, Chantal AURICCHIO, Cesare TORTI, Davide MANFRE', Laura CAPECCHI, Emanuela CALVETTI, Stefano ZANCHI
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Publication number: 20220068741Abstract: A semiconductor chip or die is mounted at a position on a support substrate. A light-permeable laser direct structuring (LDS) material is then molded onto the semiconductor chip positioned on the support substrate. The semiconductor chip is visible through the LDS material. Laser beam energy is directed to selected spatial locations of the LDS material to structure in the LDS material a pat gstern of structured formations corresponding to the locations of conductive lines and vias for making electrical connection to the semiconductor chip. The spatial locations of the LDS material to which laser beam energy is directed are selected as a function of the position the semiconductor chip which is visible through the LDS material, thus countering undesired effects of positioning offset of the chip on the substrate.Type: ApplicationFiled: August 25, 2021Publication date: March 3, 2022Applicant: STMicroelectronics S.r.l.Inventors: Pierangelo MAGNI, Michele DERAI
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Publication number: 20220068788Abstract: A warped semiconductor die is attached onto a substrate such as a leadframe by dispensing a first mass of die attach material onto an area of the substrate followed by dispensing a second mass of die attach material so that the second mass of die attach material provides a raised formation of die attach material. For instance, the second mass may be deposited centrally of the first mass. The semiconductor die is placed onto the first and second mass of die attach material with its concave/convex shape matching the distribution of the die attach material thus effectively countering undesired entrapment of air.Type: ApplicationFiled: August 25, 2021Publication date: March 3, 2022Applicants: STMicroelectronics S.r.l., STMicroelectronics SDN BHDInventors: Andrea ALBERTINETTI, Marifi Corregidor CAGUD
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Publication number: 20220069811Abstract: An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.Type: ApplicationFiled: August 26, 2021Publication date: March 3, 2022Applicant: STMicroelectronics (Grenoble 2) SASInventors: Denis COTTIN, Fabrice ROMAIN
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Publication number: 20220069837Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.Type: ApplicationFiled: July 13, 2021Publication date: March 3, 2022Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Rupesh SINGH
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Publication number: 20220065923Abstract: An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.Type: ApplicationFiled: August 19, 2021Publication date: March 3, 2022Applicant: STMicroelectronics S.r.l.Inventors: Mirko DONDINI, Roberto CRISAFULLI, Calogero Andrea TRECARICHI, Vincenzo RANDAZZO
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Publication number: 20220069110Abstract: A device includes a controllable current source connected between a first node and a first terminal coupled to a cathode of a controllable diode. A capacitor is connected between the first node and a second terminal coupled to an anode of the controllable diode. A first switch is connected between the first node and a third terminal coupled to a gate of the controllable diode. A second switch is connected between the second and third terminals. A first diode is connected between the third terminal and the second terminal, an anode of the first diode being preferably coupled to the third terminal.Type: ApplicationFiled: August 26, 2021Publication date: March 3, 2022Applicant: STMicroelectronics (Tours) SASInventor: Frederic GAUTIER
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Publication number: 20220066498Abstract: An N-bit linear feedback shift register includes P parallel chains of flip flops each having an input and output. The input is coupled to output of an XOR circuit for that parallel chain. Inputs of the XOR circuit for that parallel chain are coupled to outputs of different flip flops of the P parallel chains according to exponents of a primitive polynomial of order N?1. The flip flops of the P parallel chains of flip flops are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are respectively produced from the outputs of last flip flops of each of P parallel chains of flip flops. Readout circuitry clocked by a first clock having a frequency that is P times that of the first clock passes a different one of the P pre-LFSR outputs at each clock cycle as a LFSR output.Type: ApplicationFiled: August 4, 2021Publication date: March 3, 2022Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Abhishek Kishore KAUL, Jeet Narayan TIWARI
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Patent number: 11265004Abstract: In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.Type: GrantFiled: October 29, 2019Date of Patent: March 1, 2022Assignee: STMicroelectronics S.r.l.Inventor: Giuseppe D'Angelo
