Patents Assigned to STMicroelectronics (Crolles 2)
  • BACK-SIDE ILLUMINATED IMAGE SENSOR
    Publication number: 20190244989
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel BENOIT, Olivier HINSINGER, Emmanuel GOURVEST
  • METHOD FOR PROGRAMMING A SPLIT-GATE MEMORY CELL AND CORRESPONDING MEMORY DEVICE
    Publication number: 20190237141
    Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.
    Type: Application
    Filed: January 24, 2019
    Publication date: August 1, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Francesco LA ROSA, Marc MANTELLI, Stephan NIEL, Arnaud REGNIER
  • JUNCTION REGION BETWEEN TWO WAVEGUIDES AND ASSOCIATED METHOD OF PRODUCTION
    Publication number: 20190235166
    Abstract: A photonic integrated device includes a first waveguide and a second waveguide. The first and second waveguides are mutually coupled at a junction region which includes a bulge region. The bulge region is defined two successive etching operations using two distinct etch masks, where the first etching operation is a partial etch and the second etching operation is a complete etch.
    Type: Application
    Filed: April 3, 2019
    Publication date: August 1, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Charles BAUDOT
  • IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190229147
    Abstract: An image sensor manufacturing method includes forming a cavity in a first plate and mounting an active layer including both image sensing components and logic components to the first plate. The active layer is pressed against the first plate in a manner such that the image sensing components in the active layer are located on walls of the cavity and the logic components in the active layer are located outside of the cavity.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 25, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Yannick SANCHEZ, Emilie DELOFFRE
  • Insulating wall and method of manufacturing the same
    Patent number: 10361238
    Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Back-illuminated global-shutter image sensor
    Patent number: 10362250
    Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Guyader, Francois Roy
  • Integrated electro-optic modulator
    Patent number: 10359652
    Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 23, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Charles Baudot, Maurin Douix, Frederic Boeuf, Sébastien Cremer
  • Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit
    Patent number: 10361188
    Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: July 23, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Jean Jimenez
  • ELECTRO-OPTICAL PHASE MODULATOR
    Publication number: 20190219847
    Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 18, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Stephane MONFRAY
  • Integrated circuit with improved resistive region
    Patent number: 10354926
    Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: July 16, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Benoît Froment, Stephan Niel, Arnaud Regnier, Abderrezak Marzaki
  • Insulating wall and method of manufacturing the same
    Patent number: 10355041
    Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 16, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • METHOD OF ETCHING A CAVITY IN A STACK OF LAYERS
    Publication number: 20190214270
    Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.
    Type: Application
    Filed: January 4, 2019
    Publication date: July 11, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre BAR, Francois LEVERD, Delia RISTOIU
  • INTEGRATED FILLER CAPACITOR CELL DEVICE AND CORRESPONDING MANUFACTURING METHOD
    Publication number: 20190214341
    Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 11, 2019
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Abderrezak MARZAKI, Arnaud REGNIER, Stephan NIEL
  • Image sensor with improved quantum efficiency for infrared radiation
    Patent number: 10347677
    Abstract: An integrated image sensor with backside illumination includes a pixel. The pixel is formed by a photodiode within an active semiconductor region having a first face and a second face. A converging lens, lying in front of the first face of the active region, directs received light rays towards a central zone of the active region. At least one diffracting element, having a refractive index different from a refractive index of the active region, is provided at least partly aligned with the central zone at one of the first and second faces.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: July 9, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Axel Crocherie, Pierre Emmanuel Marie Malinge
  • Vertical quantum transistor
    Patent number: 10332982
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 25, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Guillaume C. Ribes
  • Device comprising multiple gate structures and method of simultaneously manufacturing different transistors
    Patent number: 10332808
    Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 25, 2019
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Franck Julien, Stephan Niel, Emmanuel Richard, Olivier Weber
  • BONDING PAD ARCHITECTURE USING CAPACITIVE DEEP TRENCH ISOLATION (CDTI) STRUCTURES FOR ELECTRICAL CONNECTION
    Publication number: 20190189654
    Abstract: A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sonarith CHHUN, Gregory IMBERT
  • ELECTRONIC DEVICE IMAGE SENSOR
    Publication number: 20190181176
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois ROY, Sonarith CHHUN
  • INTEGRATED CIRCUIT IMAGE SENSOR CELL WITH SKIMMING GATE IMPLEMENTED USING A VERTICAL GATE TRANSISTOR STRUCTURE
    Publication number: 20190181180
    Abstract: An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Image sensor of global shutter type
    Patent number: 10321073
    Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy