Patents Assigned to STMicroelectronics (Crolles 2)
  • IMAGE SENSOR WITH IMPROVED QUANTUM EFFICIENCY FOR INFRARED RADIATION
    Publication number: 20190280032
    Abstract: An integrated image sensor with backside illumination includes a pixel. The pixel is formed by a photodiode within an active semiconductor region having a first face and a second face. A converging lens, lying in front of the first face of the active region, directs received light rays towards a central zone of the active region. At least one diffracting element, having a refractive index different from a refractive index of the active region, is provided at least partly aligned with the central zone at one of the first and second faces.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Axel CROCHERIE, Pierre Emmanuel Marie MALINGE
  • VERTICAL PHOTODIODE
    Publication number: 20190280144
    Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles BAUDOT, Sebastien CREMER, Nathalie VULLIET, Denis PELLISSIER-TANON
  • GERMANIUM PHOTODIODE
    Publication number: 20190280146
    Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Charles BAUDOT, Sebastien CREMER, Nathalie VULLIET, Denis PELLISSIER-TANON
  • Phase-change memory
    Patent number: 10403682
    Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Morin, Philippe Brun, Laurent-Luc Chapelon
  • Optical signal splitter
    Patent number: 10401571
    Abstract: The disclosure relates to an optical splitter including two waveguides on either side of an axis. Each waveguide includes a first segment and a second segment that are closer to the axis than the rest of the waveguide. The first segments are optically coupled and the second segments are optically coupled. Each guide includes between the first and second segment, starting from the first segment, a first curved section including in succession a curvature the concavity of which is turned the side opposite the axis then a curvature the concavity of which is turned towards the axis, and starting from the second segment a second curved section including in succession a curvature the concavity of which is turned the side opposite the axis then a curvature the concavity of which is turned towards the axis. The first curved sections of the two waveguides are curved differently.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Patrick Le Maitre, Jean-Francois Carpentier
  • VERTICAL QUANTUM TRANSISTOR
    Publication number: 20190267473
    Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Guillaume C. RIBES
  • INTEGRATED CIRCUIT COMPRISING A SUBSTRATE EQUIPPED WITH A TRAP-RICH REGION, AND FABRICATING PROCESS
    Publication number: 20190267335
    Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.
    Type: Application
    Filed: February 18, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier DUTARTRE
  • Photonic interconnection switches and network integrated in an optoelectronic chip
    Patent number: 10393965
    Abstract: A photonic interconnection elementary switch is integrated in an optoelectronic chip/The switch includes first and second linear optical waveguides which intersect to form a first intersection. Two first photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. Two second photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. A third linear optical waveguide is coupled to one of the first ring resonators and one of the second ring resonators. A fourth linear optical waveguide is coupled to another of the first resonators and to another of the second ring resonators. A base switch, complex switch, and photonic interconnection network integrated in an optoelectronic chip, include at least two of the photonic interconnection elementary switches.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Michit, Patrick Le Maitre
  • Electro-optic device with multiple photonic layers and related methods
    Patent number: 10393958
    Abstract: A method for making an electro-optic device includes forming a first photonic device having a first material in a first photonic layer over a substrate layer. A second photonic layer with a second photonic device is formed over the first photonic layer and includes a second material different than the first material. A dielectric layer is formed over the second photonic layer. A first electrically conductive via extending through the dielectric layer and the second photonic layer is formed so as to couple to the first photonic device. A second electrically conductive via extending through the dielectric layer and coupling to the second photonic device is formed. A third electrically conductive via extending through the dielectric layer, the second photonic layer, and the first photonic layer is formed so as to couple to the substrate layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: August 27, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Frédéric Boeuf, Charles Baudot
  • Image sensor with high dynamic range
    Patent number: 10397503
    Abstract: A photodiode produces photogenerated charges in response to exposure to light. An integration period collects the photogenerated charges. Collected photogenerated charges in excess of an overflow threshold are passed to an overflow sense node. Remaining collected photogenerated charges are passed to a sense node. A first signal representing the overflow photogenerated charges is read from the overflow sense node. A second signal representing the remaining photogenerated charges is read from the sense node.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Emmanuel Marie Malinge, Frederic Lalanne
  • PROCESS FOR FORMING A LAYER OF A WORK FUNCTION METAL FOR A MOSFET GATE HAVING A UNIAXIAL GRAIN ORIENTATION
    Publication number: 20190259618
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. The metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition with process parameters selected so as to produce grains of material exhibiting a uniaxial grain orientation. The uniaxial grain structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Application
    Filed: February 19, 2018
    Publication date: August 22, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Florian Domengie, Pushpendra Kumar
  • BIPOLAR-TRANSISTOR DEVICE AND CORRESPONDING FABRICATION PROCESS
    Publication number: 20190259838
    Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis GAUTHIER, Julien BORREL
  • Method for managing the operation of a test mode of a logic component with restoration of the pre-test state
    Patent number: 10386414
    Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 20, 2019
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Jean-Marc Daveau, Philippe Roche, Didier Fuin
  • Formation of Ohmic contacts for a device provided with a region made of III-V material and a region made of another semiconductor material
    Patent number: 10388653
    Abstract: A production of contact zones for a transistor device including the steps of: a) forming at least one layer made of a compound based on semiconductor and metal on one or more first semiconductor region(s) of a first N-type transistor and on one or more second semiconductor region(s) of a second P-type transistor resting on a same substrate, the first regions being based on a III-V type material whereas the second semiconductor regions are based on another material different from the III-V material, the semiconductor of the compound being an N-type dopant of the III-V material, b) carrying out at least one thermal annealing so as to form on the first semiconductor regions first contact zones and on the second semiconductor regions second contact zones based on a semiconductor and metal compound while increasing the N-doping of the III-V material.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 20, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Rodriguez, Elodie Ghegin, Fabrice Nemouchi
  • DETECTION DEVICE, IN PARTICULAR INCORPORATED IN A PH METER, AND CORRESPONDING PRODUCTION PROCESS
    Publication number: 20190250124
    Abstract: A detection stage of an electronic detection device, for example a pH meter, includes an insulating region that receives an element to be analyzed. The insulating region is positioned on a sensing conductive region. A biasing stage includes an electrically conductive region which is capacitively coupled to the conductive region. The electrically conductive region is formed in an uppermost metallization level along with a further conductive region. That further conductive region is electrically connected to the sensing conductive region by a via passing through an insulating layer which insulates the electrically conductive region from the sensing conductive region.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 15, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Getenet Tesega AYELE, Stephane MONFRAY
  • Method of forming MOS and bipolar transistors
    Patent number: 10381344
    Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: August 13, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier Weber, Emmanuel Richard, Philippe Boivin
  • PNP-type bipolar transistor manufacturing method
    Patent number: 10381269
    Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 13, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Gregory Avenier
  • Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device
    Patent number: 10381478
    Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 13, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Frederic Boeuf, Olivier Weber
  • Electronic component and method of manufacturing the same
    Patent number: 10381394
    Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 13, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Nicolas Hotellier
  • METHOD FOR FORMING AN ELECTRICAL CONTACT BETWEEN A SEMICONDUCTOR FILM AND A BULK HANDLE WAFER, AND RESULTING STRUCTURE
    Publication number: 20190244857
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Didier DUTARTRE, Jean-Pierre CARRERE, Jean-Luc HUGUENIN, Clement PRIBAT, Sarah KUSTER