Patents Assigned to STMicroelectronics (Crolles 2)
  • Method for aligning electro-optic device with optical fiber array with optical grating couplers
    Patent number: 9529165
    Abstract: A method is for aligning an electro-optic device. The method may include initially positioning an optical fiber array adjacent to optical grating couplers, and actively aligning the optical fiber array relative to the optical grating couplers in a yaw direction and a roll direction to determine a yaw and roll alignment at a first operating wavelength. The method may include actively aligning the optical fiber array relative to optical grating couplers in an x direction and a y direction to determine a first x and y alignment at the first operating wavelength, determining a second operating wavelength, and actively aligning the optical fiber array again relative to the optical grating couplers in the x direction and y direction to determine a second x and y alignment at the second operating wavelength.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 27, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Patrick Lemaitre, Jean-Francois Carpentier
  • PROCESS FOR PRODUCING A CONTACT ON AN ACTIVE ZONE OF AN INTEGRATED CIRCUIT, FOR EXAMPLE PRODUCED ON AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20160372562
    Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provide and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
    Type: Application
    Filed: December 8, 2015
    Publication date: December 22, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Emmanuel Petitprez
  • ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160372510
    Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.
    Type: Application
    Filed: December 4, 2015
    Publication date: December 22, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Nicolas Hotellier
  • ESD protection thyristor adapted to electro-optical devices
    Patent number: 9523815
    Abstract: A thyristor may include a first optical waveguide segment in a semiconductor material, having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. The thyristor may further include a second optical waveguide segment in a semiconductor material, adjacent the first waveguide segment and having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. A transverse bipolar junction may be between the second longitudinal portions of the first and second waveguide segments. An electrical insulator may separate each of the first longitudinal portions from the waveguide segment adjacent thereto.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: December 20, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Robert Manouvrier, Estelle Batail
  • Support for capillary self-assembly with horizontal stabilisation, fabrication method and use
    Patent number: 9522450
    Abstract: A support is provided, including a reception zone in which the external envelope matches the shape of a plate configured to be placed on a droplet deposited at least in the reception zone in order to achieve capillary self-assembly of the plate and the support, and at least one pair of tracks that extend on the support from the reception zone and that have a lyophilic-type affinity with the droplet such that an overflow of the droplet beyond the reception zone is guided in the tracks, wherein the at least one pair of tracks includes a first track and a second track that do not have the same lyophilic-type degree of affinity with the droplet.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: December 20, 2016
    Assignees: Commissariat a' l'energie atomique et aux energies alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean Berthier, Lea Di Cioccio, Sebastien Mermoz
  • Method for forming integrated circuits on a strained semiconductor substrate
    Patent number: 9525067
    Abstract: An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: December 20, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel-Camille Bensahel, Aomar Halimaoui
  • Method for manufacturing a polycrystalline dielectric layer
    Patent number: 9525019
    Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 20, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Mickael Gros-Jean
  • Image sensor illuminated and connected on its back side
    Patent number: 9520435
    Abstract: An image sensor including a semiconductor layer; a stack of insulating layers resting on the back side of the semiconductor layer; a conductive layer portion extending along part of the height of the stack and flush with the exposed surface of the stack; laterally-insulated conductive fingers extending through the semiconductor layer from its front side and penetrating into said layer portion; laterally-insulated conductive walls separating pixel areas, these walls extending through the semiconductor layer from its front side and having a lower height than the fingers; and an interconnection structure resting on the front side of the semiconductor layer and including vias in contact with the fingers.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: December 13, 2016
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Nayera Ahmed, Michel Marty
  • Integrated structure with improved heat dissipation
    Patent number: 9520334
    Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: December 13, 2016
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS SA
    Inventors: Laurent-Luc Chapelon, Pascal Ancey, Sandrine Lhostis
  • PROCESS FOR PRODUCING MOS TRANSISTORS HAVING A LARGER CHANNEL WIDTH FROM AN SOI AND IN PARTICULAR FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20160351661
    Abstract: An integrated circuit includes a substrate with an isolation region that bounds a zone. A transistor includes a concave semiconductor region that is supported by the isolation region in a first direction and has a concavity turned to face towards the zone. The concave semiconductor region contains drain, source and channel regions. A gate region for the transistor possesses a concave portion overlapping a portion of the concave semiconductor region. A dielectric region is located between the zone of the substrate and the concave semiconductor region.
    Type: Application
    Filed: December 8, 2015
    Publication date: December 1, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Stephane Monfray, Thomas Skotnicki
  • LOW REFLECTANCE BACK-SIDE IMAGER
    Publication number: 20160351611
    Abstract: A back-side imager includes a matrix of photosites in an active layer. An interconnect layer covers the active layer. A layer of germanium is positioned between the active layer and the interconnect layer.
    Type: Application
    Filed: December 4, 2015
    Publication date: December 1, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Method of manufacturing a photonic integrated circuit optically coupled to a laser of III-V material
    Patent number: 9507089
    Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: November 29, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • TRANSISTOR WITH A LOW-K SIDEWALL SPACER AND METHOD OF MAKING SAME
    Publication number: 20160343814
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 24, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Optical waveguide to be carried by a semiconductor material including a plurality of parallel strips of alternating conductivity types and related methods
    Patent number: 9500805
    Abstract: An optical waveguide in a semiconductor material, may include, between two adjacent portions of the waveguide, a plurality of parallel strips of alternating conductivity types forming a plurality of opposing bipolar junctions between the two adjacent portions.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: November 22, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Robert Manouvrier, Patrick Lemaitre, Jean-Francois Carpentier
  • Method and structure of making enhanced UTBB FDSOI devices
    Patent number: 9502505
    Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: November 22, 2016
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Qing Liu, Thomas Skotnicki
  • Local strain generation in an SOI substrate
    Patent number: 9502558
    Abstract: Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: November 22, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Shay Reboh, Laurent Grenouillet, Cyrille Le Royer, Sylvain Maitrejean, Yves Morand
  • INTEGRATED CIRCUIT CHIP ASSEMBLED ON AN INTERPOSER
    Publication number: 20160322276
    Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Bar, Alisee Taluy, Olga Kokshagina
  • Vertical gate transistor and pixel structure comprising such a transistor
    Patent number: 9478570
    Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 25, 2016
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Jean-Robert Manouvrier, Pascal Fonteneau, Xavier Montagner
  • Method for controlling an integrated circuit
    Patent number: 9479168
    Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: October 25, 2016
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Bastien Giraud, Fady Abouzeid, Sylvain Clerc, Jean-Philippe Noel, Philippe Roche, Yvain Thonnart
  • Method of forming a strained silicon layer
    Patent number: 9460923
    Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: October 4, 2016
    Assignees: STMicroelectronics (Crolles 2) SAS, Commisariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Aomar Halimaoui, Jean-Michel Hartmann