Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

Abstract: A thermo-mechano-electric converter including a plurality of shape memory bistable elements embedded in a resilient material intimately associated with a piezoelectric material.

Abstract: A substrate of the silicon-on-insulator type is formed from an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate. A localized modification of a thickness of the semiconductor film is made so as to form a semiconductor film having different thicknesses in different regions.

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract: A method is for testing a photonic integrated circuit (IC) that includes a test structure having a test optical splitter, a test optical input, and first and second test optical outputs. A device under test (DUT) is coupled between the first test optical output and the first output of the test optical splitter. The deembedding structure includes a deembedding optical splitter, a deembedding optical input and first and second deembedding optical outputs. The method includes coupling a test probe device to the test optical inputs and outputs and the deembedding optical inputs and outputs and operating the test probe device to make at least one test measurement related to the DUT and at least one deembedding measurement. The at least one test measurement is processed with the at least one deembedding measurement to determine whether the DUT is acceptable and independent of alignment error.

Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

Abstract: A device includes a support, a three-dimensional integrated structure above the support, and a lateral encapsulation region arranged around the structure. The lateral encapsulation region includes first channels configured to make it possible to circulate a cooling fluid.

Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.

Abstract: A device for converting heat energy into electrical energy including cells, the cells including: a first cavity with one wall for contacting a heat source; a second cavity with one wall for contacting a cold source; a primary channel between the first cavity and the second cavity transporting a fluid as liquid drops, the primary channel providing transport of liquid fluid drops from the second cavity to the first cavity; at least one secondary channel between the first cavity and the second cavity transporting the fluid as a gas; a piezoelectric material provided in one of the cavities; and a fluid as a liquid and gas contained within the cell.

Abstract: A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate dielectric layer; and forming a metal hard mask on the metal layer, with the hard mask having a composition different from that of the metal layer and covering a first region of the metal layer and leaving open a second region of the metal layer. The method may also include diffusion annealing the intermediate structure obtained in the prior steps such as to make the metal atoms of the hard mask diffuse into the first region, and removal of the hard mask.

Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.

Abstract: A method of manufacturing an insulating trench including the successive steps of: a) forming, on a semiconductor substrate, a first masking structure including a layer of a first selectively-etchable material and etching a trench into the substrate; b) forming an insulating coating on the trench walls and filling the trench with doped polysilicon; c) forming a silicon oxide plug penetrating into the trench substantially all the way to the upper surface of the substrate and protruding above the upper surface of the substrate; and d) removing the layer of the first material.

Abstract: A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.

Abstract: An ESD protection device for an electro-optical device may include an optical waveguide segment being in semiconductor material and including a central zone of a first conductivity type, and first and second wings of a second conductivity type different from the first conductivity type and being integral with the central zone. The ESD protection device may include a first conduction terminal on the first wing for defining a first protection terminal, a second conduction terminal on the second wing for defining a second protection terminal, and a resistive contact structure of the first conductivity type having a transverse arm integral with the central zone, and an end in ohmic contact with the first conduction terminal, the resistive contact structure being electrically insulated from the first wing.

Abstract: A first closed enclosure defines a cavity having an inner dimension smaller than 5 mm. At least one second resiliently deformable closed enclosure is connected in fluid communication with the first enclosure. A fluid at more than 90% in the liquid state fills the first and second enclosures. A first portion of the first enclosure is in contact with a hot source of a temperature higher than the evaporation temperature of the fluid. A second portion of the first enclosure located between the first portion and the resiliently deformable closed enclosure is in contact with a cold source at a temperature lower than the condensation temperature of the fluid. An electromechanical transducer is coupled to a deformable membrane of the resiliently deformable closed enclosure.

Abstract: A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.