Patents Assigned to STMicroelectronics (Crolles 2)
  • METHOD OF PLANARIZING RECESSES FILLED WITH COPPER
    Publication number: 20150340269
    Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology.
    Type: Application
    Filed: May 7, 2015
    Publication date: November 26, 2015
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Maurice Rivoire, Viorel Balan
  • SOI integrated circuit comprising adjacent cells of different types
    Patent number: 9190334
    Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 17, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Thomas, Jerome Mazurier, Nicolas Planes, Olivier Weber
  • Method for manufacturing a suspended membrane and dual-gate MOS transistor
    Patent number: 9184295
    Abstract: A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stéphane Monfray, Thomas Skotnicki
  • PMOS TRANSISTOR WITH IMPROVED MOBILITY OF THE CARRIERS
    Publication number: 20150311277
    Abstract: A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the <110> type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel.
    Type: Application
    Filed: March 6, 2015
    Publication date: October 29, 2015
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent Fiori, Sebastien Gallois-Garreignot, Denis Rideau, Clement Tavernier
  • Method for producing an integrated imaging device with front face illumination comprising at least one metal optical filter, and corresponding device
    Patent number: 9171973
    Abstract: An integrated imaging device supports front face illumination with one or more photosensitive regions formed in a substrate. A lower dielectric region is provided over the substrate, the lower dielectric region having an upper face. A metal optical filter having a metal pattern is provided on the upper face (or extending into the lower dielectric region from the upper face). An upper dielectric region is provided on top of the lower dielectric region and metal optical filter. The lower dielectric region is at least part of a pre-metal dielectric layer, and the upper dielectric region is at least part of a metallization layer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 27, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Romain Girard Desprolet, Sandrine Lhostis, Salim Boutami, Michel Marty
  • THERMOELECTRIC GENERATOR COMPRISING A DEFORMABLE BY-LAYER MEMBRANE EXHIBITING MAGNETIC PROPERTIES
    Publication number: 20150300328
    Abstract: An electrical generator is composed of a bi-layer membrane enabling the conversion of a thermal energy into electrical energy. The bi-layer membrane is deformable and includes at least two layers having different thermal expansion coefficients. The membrane moves between positions in a reversible fashion in response to heat dissipation and as a function of two flexing temperatures. A magnetic structure associated with the membrane functions to set the flexing temperatures as a function of ambient temperature.
    Type: Application
    Filed: April 14, 2015
    Publication date: October 22, 2015
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Onoriu Puscasu, Stephane Monfray, Thomas Skotnicki, Christophe Maitre
  • Process for producing at least one through-silicon via with improved heat dissipation, and corresponding three-dimensional integrated structure
    Patent number: 9165861
    Abstract: A method for producing at least one through-silicon via inside a substrate may include forming a cavity in the substrate from a first side of the substrate until an electrically conductive portion is emerged onto. The method may also include forming an electrically conductive layer at a bottom and on walls of the cavity, and at least partly on a first side outside the cavity. The process may further include at least partially filling the cavity with at least one phase-change material. Another aspect is directed to a three-dimensional integrated structure.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: October 20, 2015
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pierre Bar, Simon Gousseau, Yann Beilliard
  • Interconnection structure for an integrated circuit
    Patent number: 9165883
    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: October 20, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • INTEGRATED CIRCUIT CHIP AND FABRICATION METHOD
    Publication number: 20150287689
    Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent-Luc Chapelon, Julien Cuzzocrea
  • INTEGRATED CIRCUIT CHIP ASSEMBLED ON AN INTERPOSER
    Publication number: 20150270192
    Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 24, 2015
    Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pierre Bar, Alisee Taluy, Olga Kokshagina
  • Air-spacer MOS transistor
    Patent number: 9117805
    Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: August 25, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Heimanu Niebojewski, Yves Morand, Cyrille Le Royer
  • Integrated circuit comprising an isolating trench and corresponding method
    Patent number: 9117876
    Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: August 25, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
  • Method of forming interconnection lines
    Patent number: 9105699
    Abstract: The invention concerns a method comprising: forming a plurality of parallel lines (502, 504, 506) of a sacrificial material over a layer of conductive material (510) of an integrated circuit, said parallel lines being separated by trenches, at least one of said lines being interrupted along its length by an opening (516) dividing it into first and second line portions (504A, 504B) separated by a space (S); forming spacers (522, 524, 526, 528, 530) in said trenches on lateral sides of said line portions and filling at least a bottom part of said opening between the line portions; removing the sacrificial material by etching; and forming interconnection lines (302, 304A, 304B, 306A, 306B, 308, 310) of said conductive material based on a pattern defined by said spacers.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: August 11, 2015
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Vincent Farys
  • Image sensor of curved surface
    Patent number: 9099603
    Abstract: A method for manufacturing an image sensor, including the steps of: forming elementary structures of an image sensor on the first surface of a semiconductor substrate; installing a layer on the first surface; defining trenches in the layer, the trenches forming a pattern in the layer; and installing, on a hollow curved substrate, the obtained device on the free surface side of the layer, the pattern being selected according to the shape of the support surface.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: August 4, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Vincent Fiori
  • Image sensor with a curved surface
    Patent number: 9099604
    Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: August 4, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: François Roy, Lucile Broussous, Julien Michelot, Jean-Pierre Oddou
  • Photosite with pinned photodiode
    Patent number: 9099366
    Abstract: A photosite is formed in a semiconductor substrate and includes a photodiode confined in a direction orthogonal to the surface of the substrate. The photodiode includes a semiconductor zone for storing charge that is formed in an upper semiconductor region having a first conductivity type and includes a main well of a second conductivity type opposite the first conductivity type and laterally pinned in a first direction parallel to the surface of the substrate. The photodiode further includes an additional semiconductor zone including an additional well having the second conductivity type that is buried under and makes contact with the main well.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: August 4, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Julien Michelot
  • Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS
    Patent number: 9099354
    Abstract: The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg?0.04?0.005*Xge<Wf1<Wfmg?0.03?0.005*Xge.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 4, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Weber, Nicolas Planes, Rossella Ranica
  • Stack of semiconductor structures and corresponding manufacturing method
    Patent number: 9093456
    Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: July 28, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Integrated circuit chip and fabrication method
    Patent number: 9093505
    Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 28, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent-Luc Chapelon, Julien Cuzzocrea
  • Method for forming an insulating trench in a semiconductor substrate and structure, especially CMOS image sensor, obtained by said method
    Patent number: 9087872
    Abstract: A structure comprising at least one DTI-type insulating trench in a substrate, the trench being at the periphery of at least one active area of the substrate forming a pixel, the insulating trench including a cavity filled with a dielectric material, the internal walls of the cavity being covered with a layer made of a boron-doped material.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: July 21, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Favennec, Arnaud Tournier, François Roy