Patents Assigned to STMicroelectronics (Crolles 2)
  • INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD
    Publication number: 20140342524
    Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
  • Three-dimensional integrated structure capable of detecting a temperature rise
    Patent number: 8890276
    Abstract: A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Method for decomposing lines of an electronic circuit
    Patent number: 8883625
    Abstract: A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Vincent Farys, Emmanuelle Serret
  • PLANAR TRANSISTORS WITH NANOWIRES COINTEGRATED ON A SOI UTBOX SUBSTRATE
    Publication number: 20140326955
    Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 6, 2014
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sylvain BARRAUD, Yves MORAND
  • Method for manufacturing insulated-gate MOS transistors
    Patent number: 8878331
    Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mickael Gros-Jean, Clement Gaumer, Emmanuel Bayard Perrin
  • Detector of biological or chemical material and corresponding array of detectors
    Patent number: 8878258
    Abstract: A detector of biological or chemical material, including a MOS transistor having its channel region inserted between upper and lower insulated gates, the upper insulated gate including a detection layer capable of generating a charge at the interface of the upper insulated gate and of its gate insulator, the thickness of the upper gate insulator being smaller than the thickness of the lower gate insulator.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics (Crolle 2) SAS
    Inventors: Stéphane Monfray, Thomas Skotnicki
  • Method for manufacturing a hybrid SOI/bulk semiconductor wafer
    Patent number: 8877600
    Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 4, 2014
    Assignees: STMicroelectronics, Inc., STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Claire Fenouillet-Beranger, Stephane Denorme, Nicolas Loubet, Qing Liu, Emmanuel Richard, Pierre Perreau
  • METHOD FOR PRODUCING A METAL-GATE MOS TRANSISTOR, IN PARTICULAR A PMOS TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20140319616
    Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 30, 2014
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sylvain Baudot, Pierre Caubet, Florian Domengie
  • Microelectromechanical device packaging with an anchored cap and its manufacture
    Patent number: 8871606
    Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: October 28, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics, N.V.
    Inventors: Clement Charbuillet, Laurent Gosset
  • SRAM read-write memory cell having ten transistors
    Patent number: 8867264
    Abstract: A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 21, 2014
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Fady Abouzeid, Sylvain Clerc
  • Device and method for measuring light energy received by at least one photosite
    Patent number: 8866062
    Abstract: A method is for measuring light energy received by a pixel including a transfer transistor, and a photodiode including a charge storage region. The method may include encapsulating the gate of the transfer transistor of the pixel in a semiconductor layer, at least one part of which includes a hydrogenated amorphous semiconductor. The method also may include grounding the charge storage region of the pixel, and determining the drift over time in the magnitude of the drain-source current of the transfer transistor.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: October 21, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Serge Blonkowski, Diana Lopez
  • Method for manufacturing an integrated circuit comprising vias crossing the substrate
    Patent number: 8860186
    Abstract: A method for forming an integrated circuit including the steps of: forming electronic components on a first surface of a substrate; forming a stack of interconnection levels on the first surface, each interconnection level including conductive tracks separated by an insulating material; forming at least one hole from a second surface of the substrate, opposite to the first surface, the hole stopping on one of the conductive tracks; depositing, on the walls and the bottom of the hole, a conductive layer and filling the remaining space with a filling material; and forming, in an interconnection level or at the surface of the interconnection stack, and opposite to said at least one hole, at least one region of a material having a modulus of elasticity greater than 50 GPa and an elongation at break greater than 20%, insulated from the conductive tracks.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Mohamed Bouchoucha, Laurent-Luc Chapelon
  • Antenna array for transmission/reception device for signals with a wavelength of the microwave, millimeter or terahertz type
    Patent number: 8860628
    Abstract: Transmission/reception device for signals having a wavelength of the microwaves, millimeter or terahertz type, comprising an antenna array. The antenna array comprises a first group of first omni-directional antennas and a second group of second directional antennas disposed around the first group of antennas.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Andreia Cathelin, Mathieu Egot, Romain Pilard, Daniel Gloria
  • Integrated circuit with protection from copper extrusion
    Patent number: 8853760
    Abstract: An integrated circuit may include an element placed in an insulating region adjacent to a copper metallization level and including a barrier layer in contact with a metallization level. The element may be electrically connected to and spaced away from a copper line of the metallization level by way of an electrical link passing through the barrier layer and including an electrically conductive material different from copper in direct contact with the copper line.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sébastien Cremer, Sébastien Gaillard
  • Image sensor pixel circuit
    Patent number: 8853755
    Abstract: A pixel circuit of an image sensor includes a sense node for storing a charge transferred from one or more photodiodes, a source follower transistor having its gate coupled to the sense node and its source node coupled to an output line of the pixel circuit via a read transistor, wherein a body contact of the source follower transistor is connected to the output line.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: October 7, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Frédéric Barbier, François Roy
  • INTEGRATED DEVICE OF A CAPACITIVE TYPE FOR DETECTING HUMIDITY, IN PARTICULAR MANUFACTURED USING A CMOS TECHNOLOGY
    Publication number: 20140291778
    Abstract: An integrated capacitive-type humidity sensor formed in a semiconductor chip integrating a sensing capacitor and a reference capacitor. Each of the sensing and reference capacitors have at least a first electrode and at least a second electrode, the first and second electrodes of each of the sensing and reference capacitors being arranged at distance and mutually insulated. A hygroscopic layer extends on the sensing and reference capacitors and a conductive shielding region extends on the reference capacitor but not on the sensing capacitor.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 2, 2014
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.
    Inventors: Michele Vaiana, Daniele Casella, Giuseppe Bruno, Rosario Cariola, Benoit Gautheron
  • Process for generating electrical energy in a semiconductor device and the corresponding device
    Patent number: 8847059
    Abstract: Electrical energy is generated in a device that includes an integrated circuit which produces thermal flux when operated. A substrate supports the integrated circuit. A structure is formed in the substrate, that structure having a semiconductor p-n junction thermally coupled to the integrated circuit. Responsive to the thermal flux produced by the integrated circuit, the structure generates electrical energy. The generated electrical energy may be stored for use by the integrated circuit.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: September 30, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Thomas Skotnicki, Stephane Monfray
  • Integrated circuit with a self-programmed identification key
    Patent number: 8848417
    Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 30, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Emmanuel Petitprez
  • SUPPORT FOR CAPILLARY SELF-ASSEMBLY WITH HORIZONTAL STABILISATION, FABRICATION METHOD AND USE
    Publication number: 20140283367
    Abstract: Support comprising a reception zone in which the external envelope matches the shape of a plate (P2) designed to be placed on a droplet deposited at least in the reception zone in order to achieve capillary self-assembly of the plate and the support, and at least one pair of tracks (T11, T12) that extend on the support from the reception zone and that have a lyophilic type affinity with the droplet such that an overflow of the droplet beyond the reception zone is guided in the tracks, characterised in that the at least one pair of tracks comprises a first track (T11) and a second track (T12) that do not have the same lyophilic type degree of affinity with the droplet.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 25, 2014
    Applicants: STMICROELECTRONICS (CROLLES 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Jean Berthier, Lea Di Cioccio, Sebastien Mermoz
  • Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method
    Patent number: 8841749
    Abstract: A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 23, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Sylvain Joblot, Alexy Farcy, Jean-Francois Carpentier, Pierre Bar