Patents Assigned to STMicroelectronics (Crolles 2)
  • SEMICONDUCTOR DEVICE COMPRISING A CRACK STOP STRUCTURE
    Publication number: 20140091451
    Abstract: A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.
    Type: Application
    Filed: September 20, 2013
    Publication date: April 3, 2014
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Delpech, Eric Sabouret, Sebastien Gallois-Garreignot
  • Charge transfer photosite
    Patent number: 8686483
    Abstract: A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 1, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Michelot, Francois Roy, Frederic Lalanne
  • Imaging device with charge collection zone and charge storage zone
    Patent number: 8680453
    Abstract: Imaging device comprising at least one photosite comprising a charge storage semiconductor zone, a charge collection semiconductor zone and transfer means designed to permit charge transfer between the charge storage zone and the charge collection zone, characterized in that the charge storage semiconductor zone comprises a lower semiconductor zone and a conduction channel buried beneath the upper surface of the photosite and connecting said lower semiconductor zone to the charge collection zone.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: François Roy
  • METHOD FOR MANUFACTURING BAW RESONATORS ON A SEMICONDUCTOR WAFER
    Publication number: 20140075726
    Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 20, 2014
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: David Petit, Sylvain Joblot, Pierre Bar, Jean-Francois Carpentier, Pierre Dautriche
  • Image sensor with reduced optical crosstalk
    Patent number: 8674283
    Abstract: A method of fabricating an image sensor includes the steps of: forming at least two photosites in a semiconductor substrate; forming a trench between the photosites; forming a thin liner on at least the sidewalls of the trench; depositing a conductive material having a first refractive index in the trench; and forming a region surrounded by the conductive material and having a second refractive index lower than the first index of refraction within the conductive material in the trench.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 18, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Francois Roy, Flavien Hirigoyen, Julien Michelot
  • Substrate provided with a semi-conducting area associated with two counter-electrodes and device comprising one such substrate
    Patent number: 8674443
    Abstract: A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 18, 2014
    Assignees: Commissariat à l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Coronel, Claire Fenouillet-Beranger, Stephane Denorme, Olivier Thomas
  • Method for formation of an electrically conducting through via
    Patent number: 8673740
    Abstract: A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Cuzzocrea, Laurent-Luc Chapelon
  • Method of assembling two integrated circuits and corresponding structure
    Patent number: 8674517
    Abstract: A semiconductor device includes an assembly of two integrated circuits. The assembly has a layer of photoresist filling the space between the two integrated circuits, and at least one electrically conducting pillar within the resist and electrically coupling the two integrated circuits.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: March 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent-Luc Chapelon, Mohamed Bouchoucha
  • METHOD FOR MANUFACTURING A SUSPENDED MEMBRANE AND DUAL-GATE MOS TRANSISTOR
    Publication number: 20140070317
    Abstract: A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.
    Type: Application
    Filed: November 12, 2013
    Publication date: March 13, 2014
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Stéphane Monfray, Thomas Skotnicki
  • PHASE-CHANGE MEMORY CELL
    Publication number: 20140070163
    Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a first region adjacent to a second region itself adjacent to at least one third region, the first, second, and third regions each extending from the upper electrode to the lower electrode, the crystallization temperature of the second region ranging between that of the first region and that of the third region, and the melting temperatures of the first, second, and third regions being substantially identical.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 13, 2014
    Applicants: Commissariat à I'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Francois Nodin, Veronique Sousa, Sandrine Lhostis
  • PHASE-CHANGE MEMORY CELL
    Publication number: 20140070158
    Abstract: A memory cell including a via made of a phase-change material arranged between a lower electrode and an upper electrode, wherein the via includes a central region laterally surrounded with a peripheral region, the crystallization and melting temperatures of the central region being respectively lower than those of the peripheral region.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 13, 2014
    Applicants: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Francois Nodin, Veronique Sousa, Sandrine Lhostis
  • Method for manufacturing a polycrystalline dielectric layer
    Patent number: 8667654
    Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: March 11, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Mickael Gros-Jean
  • Imaging device in particular of the CMOS time delay and integration type
    Patent number: 8669510
    Abstract: An imaging device may be formed in a semiconductor substrate including a matrix array of photosites extending in a first direction and a second direction. The imaging device may include a transfer module configured to transfer charge in the first direction and an extraction module configured to extract charge in the second direction.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 11, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: François Roy
  • Single-port memory with addresses having a first portion identifying a first memory block and a second portion identifying a same rank in first, second, third, and fourth memory blocks
    Patent number: 8671262
    Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocks of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 11, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Cedric Minne
  • Image sensor photodiode
    Patent number: 8659109
    Abstract: An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: February 25, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: François Roy
  • Method for creating a photolithography mask
    Patent number: 8656320
    Abstract: A method for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set includes first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method includes a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Christian Gardin
  • Simplified copper-copper bonding
    Patent number: 8647983
    Abstract: A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: February 11, 2014
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Lea Di Cioccio, Pierric Gueguen, Maurice Rivoire
  • Multidirectional two-phase charge-coupled device
    Patent number: 8643063
    Abstract: A charge transfer device formed in a semiconductor substrate and including an array of electrodes distributed in rows and columns, wherein: each electrode is formed in a cavity with insulated walls formed of a groove which generally extends in the row direction, having a first end closer to an upper row and a second end closer to a lower row; and the electrodes of two adjacent rows are symmetrical with respect to a plane orthogonal to the sensor and comprising the direction of a row.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: February 4, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: François Roy
  • METHOD OF FABRICATING A DEVICE WITH A CONCENTRATION GRADIENT AND THE CORRESPONDING DEVICE
    Publication number: 20140027886
    Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 30, 2014
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Daniel-Camille Bensahel, Yves Morand
  • METHOD FOR MANUFACTURING A POLYCRYSTALLINE DIELECTRIC LAYER
    Publication number: 20140021586
    Abstract: A method manufactures a capacitor having polycrystalline dielectric layer between two metallic electrodes. The dielectric layer is formed by a polycrystalline growth of a dielectric metallic oxide on one of the metallic electrodes. At least one polycrystalline growth condition of the dielectric oxide is modified during the formation of the polycrystalline dielectric layer, which results in a variation of the polycrystalline properties of the dielectric oxide within the thickness of said layer.
    Type: Application
    Filed: September 25, 2013
    Publication date: January 23, 2014
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Mickael Gros-Jean