Patents Assigned to STMicroelectronics (Crolles 2)
  • Patent number: 8627238
    Abstract: A method for designing a photolithography mask and a light source may include designing an initial photolithography mask and an initial light source using an initial target pattern corresponding to a desired target pattern in a resist layer. The method may also include designing a new target pattern and designing a new photolithography mask and/or a new light source using the new target pattern.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Clovis Alleaume
  • Publication number: 20140004644
    Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.
    Type: Application
    Filed: April 8, 2013
    Publication date: January 2, 2014
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
  • Patent number: 8603887
    Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 10, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, International Business Machines Corporation
    Inventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
  • Patent number: 8586445
    Abstract: A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: November 19, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stéphane Monfray, Thomas Skotnicki
  • Publication number: 20130292952
    Abstract: A device for converting thermal energy into electric energy intended to be used in combination with a hot source including: a capacitor of variable capacitance, including two electrodes separated by an electrically-insulating material, one of these electrodes being deformable and being associated with an element forming a bimetallic strip, said bimetallic strip including at least two layers of materials having different thermal expansion coefficients, said bimetallic strip being free to deform when it is submitted to the heat of said hot source; a second capacitor having a first electrode connected to a first electrode of said capacitor of variable capacitance; a harvesting circuit electrically connected between the second electrode of the capacitor of variable capacitance and the second electrode of the second capacitor, said harvesting circuit being capable of conducting the current flowing between said second electrodes.
    Type: Application
    Filed: April 30, 2013
    Publication date: November 7, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Thomas Skotnicki, Onoriu Puscasu, Stéphan Monfray
  • Publication number: 20130292823
    Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.
    Type: Application
    Filed: April 24, 2013
    Publication date: November 7, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Patent number: 8575011
    Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: November 5, 2013
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel-Camille Bensahel, Yves Morand
  • Publication number: 20130288450
    Abstract: A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO2 layer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiO2 layer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiO2 layer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiO2 layer; depositing a second silicon nitride layer and filling the trench with SiO2; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed.
    Type: Application
    Filed: April 2, 2013
    Publication date: October 31, 2013
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Daniel Benoit, Laurent Favennec
  • Publication number: 20130280549
    Abstract: A method of forming at least one curved plate having first and second layers, the first layer being formed of a first material and the second layer being formed of a second material, the method including forming one or more blocks of a fusible material on a surface of a substrate; baking the one or more blocks to deform their shape; and depositing the first and second materials over the one or more deformed blocks to form the first and second layers.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 24, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: STMicroelectronics (Crolles 2) SAS
  • Patent number: 8562934
    Abstract: A surface of a substrate comprising microcavities leading out of the substrate is placed in contact with an aqueous solution comprising a plurality of suspended particles and a fabric. Perpendicular pressure is applied the expanse of the substrate between the fabric and the surface of the substrate, and relative movement of the fabric and the surface is applied to the expanse of the substrate. At least one particle is thus fed into each microcavity, therein forming a porous material that is a catalyst material for nanothread or nanotube growth.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: October 22, 2013
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Christophe Coiffic, Maurice Rivoire
  • Patent number: 8565030
    Abstract: A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 22, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, Centre National de la Recherche Scientifique
    Inventors: Fady Abouzeid, Sylvain Clerc, Philippe Roche
  • Publication number: 20130270662
    Abstract: A method for manufacturing an image sensor, including the steps of: forming elementary structures of an image sensor on the first surface of a semiconductor substrate; installing a handle on the first surface; defining trenches in the handle, the trenches forming a pattern in the handle; and installing, on a hollow curved substrate, the obtained device on the free surface side of the handle, the pattern being selected according to the shape of the support surface.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 17, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Vincent Fiori
  • Publication number: 20130273440
    Abstract: A housing includes a body with a first silicon element and a second porous silicon element, at least one first cavity provided in the porous silicon element, a first electrically conducting contact area electrically coupled to at least a portion of at least one internal wall of the at least one first cavity, and a second electrically conducting contact area electrically coupled to a different portion of the at least one internal wall of the second porous silicon element of the at least one first cavity, wherein the two contact areas are electrically isolated from each other.
    Type: Application
    Filed: December 12, 2011
    Publication date: October 17, 2013
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Pascale Mazoyer, Aomar Halimaoui
  • Patent number: 8552369
    Abstract: A method of obtaining an elemental concentration profile of a sample using x-ray photon spectroscopy measurements is described. Each measurement relates to a different depth in the sample. The sample is shaped to provide access to different depths thereof. Measurements are obtained at respective positions on a bevelled surface exposing material at each of the depths. The method involves fitting the measurements to a mathematical function, dividing the function into a plurality of equal depth wise slices, determining the elemental concentration for the slice corresponding to the thinnest part of the bevel, and then iteratively determining the contribution of each successive slice to the intensity value as being the intensity value measured for that slice minus the intensity value determined to have been contributed by each preceding slice. According to preferred embodiments, a surface correction factor compensating surface effect phenomena is applied to the concentration value calculated for each slice.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 8, 2013
    Assignees: International Business Machines Corporation, STMicroelectronics (Crolles 2) SAS
    Inventors: Nicolas Breil, Jerome Bienacel
  • Publication number: 20130257219
    Abstract: An energy harvester including first and second sheets; and a plurality of walls, each wall being sandwiched between the first and second sheets and surrounding a cavity, wherein each cavity houses at least one curved plate adapted to change from a first shape to a second shape when its temperature reaches a first threshold and to return to the first shape when its temperature falls to a second threshold lower than said first threshold.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 3, 2013
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Stéphane MONFRAY, Thomas Skotnicki, Christophe Maitre, Onoriu Puscasu
  • Patent number: 8545634
    Abstract: A system for cleaning a conditioning device to improve the efficiency of the conditioning of a polishing pad using the conditioning device as part of a chemical-mechanical polishing process, the system comprising a conditioning device; a fluid dispenser arranged to dispense a fluid on the conditioning device; and an acoustic nozzle arranged to emit a megasonic or ultrasonic signal at the conditioning device while the fluid dispenser is dispensing the fluid on the conditioning device.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: October 1, 2013
    Assignees: Freescale Semiconductor, Inc., STMicroelectronics SRL, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Marc Lafon, Silvio Delmonaco, Sebastien Petitdidier
  • Publication number: 20130240999
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 19, 2013
    Applicants: NXP B.V., STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Alexandre Mondot, Markus Mueller, Thomas Kormann
  • Patent number: 8536027
    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 17, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Aomar Halimaoui, Daniel Bensahel
  • Patent number: 8531567
    Abstract: An image sensor including a first pixel positioned between second and third pixels, each of the first, second and third pixels comprising a photodiode region surrounded by an isolation trench; a first charge transfer gate comprising a first column electrode surrounded by an insulating layer and positioned in an opening of the isolation trench between the first and second pixels, the first column electrode being configured to receive a first transfer voltage signal; and a second charge transfer gate including a second column electrode surrounded by an insulating layer and positioned in an opening of the isolation trench between the first and third pixels, the second column electrode being configured to receive a second transfer voltage signal.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: September 10, 2013
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Frédéric Barbier
  • Patent number: 8524522
    Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 3, 2013
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima