Abstract: An apparatus comprises an array of vertical-cavity surface-emitting lasers. Each of the vertical-cavity surface-emitting lasers is configured to be a source of light. The apparatus also comprises an optical arrangement configured to receive light from a plurality of the vertical-cavity surface-emitting lasers and to output a plurality of light beams.
Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 ?m, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.
Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
Type:
Application
Filed:
October 26, 2023
Publication date:
February 22, 2024
Applicants:
STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.
Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.
Abstract: An over-voltage protection circuit and methods of operation are provided. In one embodiment, a method includes monitoring a voltage at an output of a rectifier, a voltage at an output of a voltage regulator, or a combination thereof. The method further includes determining the over-voltage condition based on the monitoring; and in response to determining the over-voltage condition, regulating the voltage at the output of the rectifier in accordance with a voltage difference between the voltage at the output of the rectifier and the voltage at the output of the voltage regulator.
Type:
Grant
Filed:
January 23, 2023
Date of Patent:
February 20, 2024
Assignee:
STMicroelectronics Asia Pacific Pte Ltd.
Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.
Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.
Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.
Type:
Grant
Filed:
June 9, 2022
Date of Patent:
February 20, 2024
Assignees:
STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
Inventors:
Daniele Mangano, Andrei Tudose, Francesco Clerici, Pasquale Butta'
Abstract: An embodiment dashboard voice control system for a motorcycle comprises receiver circuitry to receive voice-generated signals, command recognition circuitry to recognize voice-generated command signals for a motorcycle dashboard out of the voice-generated signals received at the receiver circuitry as well as command implementation circuitry to implement motorcycle dashboard actions as a function of voice-generated command signals recognized by the command recognition circuitry.
Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.
Type:
Grant
Filed:
May 20, 2021
Date of Patent:
February 20, 2024
Assignees:
STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS
Inventors:
Eric Sabouret, Krysten Rochereau, Olivier Hinsinger, Flore Persin-Crelerot
Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
Type:
Grant
Filed:
June 9, 2022
Date of Patent:
February 20, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Daniele Mangano, Francesco Clerici, Pasquale Butta'
Abstract: A circuit device includes a directional coupler with a first port receiving a radiofrequency signal, a second port outputting a signal in response to signal received by the first port, and a third port outputting a signal in response to a reflection of the signal at the second port. An impedance matching network is connected between the second port and an antenna. The impedance matching network includes fixed inductive and capacitive components and a single variable inductive or capacitive component. A diode coupled to the third port of the coupler generates a voltage at a measurement terminal which is processed in order to select and set the inductance or capacitance value of the variable inductive or capacitive component.
Type:
Grant
Filed:
February 24, 2023
Date of Patent:
February 20, 2024
Assignee:
STMicroelectronics (Tours) SAS
Inventors:
Jean Pierre Proot, Pascal Paillet, Francois Dupont
Abstract: In an embodiment a circuit includes an inertial measurement unit configured to be oscillated via a driving signal provided by driving circuitry, a lock-in amplifier configured to receive a sensing signal from the inertial measurement unit and a reference demodulation signal which is a function of the driving signal and provide an inertial measurement signal based on the sensing signal, wherein the reference demodulation signal is affected by a variable phase error, phase meter circuitry configured to receive the driving signal and the sensing signal and provide, as a function of a phase difference between the driving signal and the sensing signal, a phase correction signal for the reference demodulation signal and a correction node configured to apply the phase correction signal to the reference demodulation signal so that, in response to the phase correction signal being applied to the reference demodulation signal, the phase error is maintained in a vicinity of a reference value.
Type:
Grant
Filed:
May 20, 2022
Date of Patent:
February 20, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Giacomo Langfelder, Leonardo Gaffuri Pagani, Luca Guerinoni, Luca Giuseppe Falorni, Patrick Fedeli, Paola Carulli
Abstract: According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.
Type:
Grant
Filed:
December 3, 2021
Date of Patent:
February 20, 2024
Assignees:
STMicroelectronics (Alps) SAS, STMicroelectronics France
Abstract: A communication circuit supports a first communication protocol and a second communication protocol that is different from the first communication protocol. A number of signals include first signals conveying first information messages and second signals conveying second information messages. The first information messages include a repetitive message having fixed repeated content and the second information messages include a non-repetitive message having variable content. The first signals and the second signals are transmitted via the communication circuit using the first communication protocol for the first signals and the second communication protocol for the second signals.
Type:
Grant
Filed:
August 30, 2019
Date of Patent:
February 20, 2024
Assignee:
STMicroelectronics S.r.l.
Inventors:
Lorenzo Guerrieri, Angelo Poloni, Edoardo Lauri
Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage config
Type:
Grant
Filed:
February 8, 2022
Date of Patent:
February 20, 2024
Assignees:
STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SAS
Inventors:
Antonino Conte, Alin Razafindraibe, Francesco Tomaiuolo, Thibault Mortier
Abstract: A microelectromechanical button device is provided with a detection structure having: a substrate of semiconductor material with a front surface and a rear surface; a buried electrode arranged on the substrate; a mobile electrode, arranged in a structural layer overlying the substrate and elastically suspended above the buried electrode at a separation distance so as to form a detection capacitor; and a cap coupled over the structural layer and having a first main surface facing the structural layer and a second main surface that is designed to be mechanically coupled to a deformable portion of a case of an electronic apparatus of a portable or wearable type.
Type:
Application
Filed:
August 1, 2023
Publication date:
February 15, 2024
Applicant:
STMICROELECTRONICS S.r.l.
Inventors:
Federico VERCESI, Gabriele GATTERE, Giorgio ALLEGATO, Mikel AZPEITIA URQUIA, Alessandro DANEI