Patents Assigned to STMicroelectronics (Crolles 2)
  • Publication number: 20240056091
    Abstract: An integrated circuit includes a plurality of ADC channels. During a calibration process of the ADC channels, the integrated circuit utilizes derivative filters to calculate a phase difference between the ADC channels. During a calibration process, the integrated circuit utilizes clock phase alignment circuits to align the phases of the ADC channels based on the outputs of the derivative filters.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 15, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Jeet Narayan TIWARI
  • Publication number: 20240053202
    Abstract: The present description concerns a polarimetric image sensor formed inside and on top of a semiconductor substrate, the second comprising a plurality of pixels, each comprising: —a photosensitive region formed in the semiconductor substrate; —a diffraction structure formed on the side of an illumination surface of the photosensitive region; and —a polarization structure formed on the side of the diffraction structure opposite to the photosensitive region.
    Type: Application
    Filed: March 17, 2023
    Publication date: February 15, 2024
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Jerome VAILLANT, Francois DENEUVILLE, Axel CROCHERIE, Alain OSTROVSKY
  • Patent number: 11897763
    Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Sismundo Talledo
  • Patent number: 11901894
    Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Elias El Haddad, Tanguy Tromelin, Patrick Bougant, Christophe Matheron
  • Patent number: 11901919
    Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Abhishek Jain, Sharad Gupta
  • Patent number: 11901216
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Gouraud, Delia Ristoiu
  • Patent number: 11898943
    Abstract: A stress sensor includes: a substrate, having a face and a recess, open to the face; and a sensor chip of semiconductor material, housed in the recess and bonded to the substrate, the sensor chip being provided with a plurality of sensing components of piezoresistive material. The substrate has a thickness which is less by at least one order of magnitude with respect to a main dimension of the face. Further, the sensor chip has a thickness which is less by at least one order of magnitude with respect to the thickness of the substrate, and a Young's module of the substrate and a Young's module of the sensor chip are of the same order of magnitude.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 13, 2024
    Assignee: STMICROELECTRONICS S.r.L.
    Inventor: Santo Alessandro Smerzi
  • Patent number: 11901278
    Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Pierre Carrere, Francois Guyader
  • Patent number: 11901819
    Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Sebastien Ortet, Olivier Lauzier
  • Patent number: 11901863
    Abstract: An oscillator circuit includes a total of N (N?2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: February 13, 2024
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Simone Spataro, Salvatore Coffa, Egidio Ragonese
  • Patent number: 11900240
    Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: February 13, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Nitin Chawla, Giuseppe Desoli, Manuj Ayodhyawasi, Thomas Boesch, Surinder Pal Singh
  • Patent number: 11901900
    Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Kailash Kumar, Manoj Kumar
  • Patent number: 11898989
    Abstract: A MEMS device for detecting particulate and gases in the air, comprising: a first semiconductor body; a second semiconductor body with a first surface facing a first surface of the first semiconductor body; and a first spacer element and a second spacer element, which extend between the first surfaces of the semiconductor bodies so as to arrange them at a distance apart from one another and define a first duct. The MEMS device further comprises at least one of the following: a first particulate sensor comprising a first emitter unit for generating acoustic waves in the first duct, and a first particulate-detection unit for detecting the particulate, the first emitter unit and the first particulate-detection unit facing one another through the first duct; and a first gas sensor, which faces the first duct and is configured to detect said gases in the air present in the first duct.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: February 13, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Francesco Foncellino, Luigi Barretta
  • Patent number: 11901865
    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Jain
  • Patent number: 11901381
    Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Andrej Suler
  • Publication number: 20240043263
    Abstract: A method for manufacturing an optical microelectromechanical device, includes forming, in a first wafer of semiconductor material having a first surface and a second surface, a suspended mirror structure, a fixed structure surrounding the suspended mirror structure, elastic supporting elements extending between the fixed structure and the suspended mirror structure, and an actuation structure coupled to the suspended mirror structure. The method continues with forming, in a second wafer, a chamber delimited by a bottom wall having a through opening, and bonding the second wafer to the first surface of the first wafer and bonding a third wafer to the second surface of the first wafer so that the chamber overlies the actuation structure, and the through opening is aligned to the suspended mirror structure, thus forming a device composite wafer. The device composite wafer is diced to form an optical microelectromechanical device.
    Type: Application
    Filed: September 11, 2023
    Publication date: February 8, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Luca SEGHIZZI, Nicolo' BONI, Laura OGGIONI, Roberto CARMINATI, Marta CARMINATI
  • Publication number: 20240045458
    Abstract: Provided are techniques for detecting a short circuit fault at an output of a regulator and protecting the regulator from the short circuit fault. An error amplifier receives a reference voltage and a feedback voltage and compares comparing the reference voltage with the feedback voltage for driving a power transistor of the regulator. A modification stage compares an output voltage of the voltage regulator with a fault reference voltage and in response to determining that the output voltage of the voltage regulator is less than the fault reference voltage, drives the power transistor using an internal node of the error amplifier by changing states of a first switch and a second switch and supplies the reference voltage to both the first and second inputs of the error amplifier by changing states of a third switch and a fourth switch.
    Type: Application
    Filed: July 21, 2023
    Publication date: February 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Zubair KHAN, Sandeep KAUSHIK
  • Publication number: 20240045001
    Abstract: An electronic device includes a magnetometer that outputs magnetometer sensor signals and a gyroscope that outputs gyroscope sensor signals. The electronic device includes a magnetometer calibration module that calibrates the magnetometer utilizing the gyroscope sensor signals. The electronic device generates a first magnetometer calibration parameter based on a Kalman filter process. The electronic device generates a second magnetometer calibration parameter based on a least squares estimation process.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Mahaveer JAIN, Mahesh CHOWDHARY
  • Publication number: 20240045030
    Abstract: A LIDAR optical unit includes a photonic-integrated-circuit (PIC) affixed to a carrier. The PIC includes an input coupler and an array of output couplers, with a switchable optical network connecting the input coupler to different selected ones of the array of output couplers. A laser source is mounted to the PIC adjacent the input coupler such that laser light generated by the laser source is injected into the input coupler. An optical stack is mounted to the PIC adjacent the array of output couplers to receive laser light extracted from the switchable optical network by the array of output couplers. The optical stack includes an array of microlenses positioned so that a bottom surface thereof is mounted to the PIC, and an array of microprisms is stacked on the array of microlenses so that a bottom surface thereof is mounted to a top surface of the array of microlenses.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventor: Antonio FINCATO
  • Publication number: 20240043265
    Abstract: Electronic device including: a MEMS sensor device including a functional structure which transduces a chemical or physical quantity into a corresponding electrical quantity; a cap including a semiconductive substrate; and a bonding dielectric region, which mechanically couples the cap to the MEMS sensor device. The cap further includes a conductive region, which extends between the semiconductive substrate and the MEMS sensor device and includes: a first portion, which is arranged laterally with respect to the semiconductive substrate and is exposed, so as to be electrically coupleable to a terminal at a reference potential by a corresponding wire bonding; and a second portion, which contacts the semiconductive substrate.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 8, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Giorgio ALLEGATO, Silvia NICOLI, Anna ALESSANDRI, Matteo GARAVAGLIA