Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.

Abstract: A stator for an electric actuator or motor, including: a solid body; a ferromagnetic core region between the layers of semiconductor material, electrically insulated from the layers of semiconductor material; a plurality of conductive through vias through the solid body; a first plurality of conductive strips, which extend parallel to one another above the core; and a second plurality of conductive strips, which extend parallel to one another above the core and opposite to the first plurality of conductive strips; wherein the first plurality of conductive strips, the plurality of conductive through vias, and the second plurality of conductive strips form a winding or coil of the stator.

Abstract: A power MOSFET device includes a semiconductor body having a first main surface. The semiconductor body includes an active area facing the first main surface. The power MOSFET device includes an isolated-gate structure, which extends over the active area and includes a gate-oxide layer, which is made of insulating material and extends over the first main surface, and a gate region buried in the gate-oxide layer so as to be electrically insulated from the semiconductor body. The gate region includes a gate layer of polysilicon and at least one first silicide electrical-modulation region and one second silicide electrical-modulation region, which extend in the gate layer so as to face a top surface of the gate layer and to be arranged alongside one another and spaced apart from one another in a first plane.

Abstract: A half bridge switching power stage includes high/low side switches driven in response to a cycle-by-cycle protected driving signal derived from a PWM signal. Signals indicative of detected over-currents at said high/low side switches are processed to output the cycle-by-cycle protected driving signal, when the signal indicative of the detected over-current indicates, during a time interval within which the high/low side switch is turned on, that current flowing in the turned on high/low side switch crosses a given threshold, as an inverted PWM signal by turning off the turned on high/low side switch, and otherwise outputting said cycle-by-cycle protected driving signal as a not inverted PWM signal. An anomaly detection circuit receives the signals indicative of the over-current and switches off both the high/low side switches when an anomaly is detected in a pattern of over-current events in the signals indicative of the over-current.

Abstract: Cantilever probes are produced for use in a test apparatus of integrated electronic circuits. The probes are configured to contact corresponding terminals of the electronic circuits to be tested during a test operation. The probe bodies are formed of electrically conductive materials. On a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region is formed having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: The detection structure for a MEMS accelerometer is formed by a substrate; a first movable mass and a second movable mass which extend at a distance from each other, suspended on the substrate and which are configured to undergo a movement, with respect to the substrate, in response to an acceleration. The detection structure also has a first movable electrode integral with the first movable mass; a second movable electrode integral with the second movable mass; a first fixed electrode integral with the substrate and configured to form, with the first movable electrode, a first variable capacitor; and a second fixed electrode integral with the substrate and configured to form, with the second movable electrode, a second variable capacitor. The detection structure has an insulation region, of electrically insulating material, which is suspended on the substrate and extends between the first movable mass and the second movable mass.

Abstract: A MEMS device comprising: a semiconductor body defining a main cavity and forming an anchorage structure; and a first deformable structure having a first end and a second end that are opposite to one another along a first axis, the first deformable structure being fixed to the anchorage structure via the first end so as to be suspended over the main cavity. The second end is configured to oscillate, with respect to the anchorage structure, along a second axis. The first deformable structure comprises a main body having a first outer surface and a second outer surface, and a piezoelectric structure, which extends over the first outer surface. The main body comprises a bottom portion and a top portion that delimit along the second axis a first buried cavity aligned with the piezoelectric structure along the second axis, wherein a maximum thickness of the top portion of the main body along the second axis is smaller than a minimum thickness of the bottom portion of the main body along the second axis.

Abstract: A device includes a single photon avalanche diode in a portion of a substrate, wherein the portion has an octagonal profile. The octagonal profile is delimited by a wall forming an octagonal contour around the portion. The device further includes an array of diodes, wherein each diode is located in a corner between four adjacent single photon avalanche diodes. Each single photon avalanche diode further includes a doped anode region. A shallow trench isolation is formed in each doped anode region. A polysilicon line forming a resistor is supported at the upper surface of the shallow trench isolation.

Abstract: An optical sensor includes pixels. Each pixel has a photodetector. A readout circuit performs a process over an exposure time where the photodetector is connected to a reverse bias voltage supply to reset a voltage across the photodetector, and the photodetector is disconnected from the reverse bias voltage supply until that the voltage across the photodetector decreases in response to received ambient light. An ambient light level is then determine an based on a number of times the voltage across the photodetector is reset over the exposure time.

Abstract: A device includes a single photon avalanche diode in a substrate and a resistor. The resistor is provided resting on an insulating trench located in a doped anode region of the single photon avalanche diode.

Abstract: A device includes a controllable current source connected between a first node and a first terminal coupled to a cathode of a controllable diode. A capacitor is connected between the first node and a second terminal coupled to an anode of the controllable diode. A first switch is connected between the first node and a third terminal coupled to a gate of the controllable diode. A second switch is connected between the second and third terminals. A first diode is connected between the third terminal and the second terminal, an anode of the first diode being preferably coupled to the third terminal.

Abstract: A thermoelectric generator includes a substrate and one or more thermoelectric elements on the substrate and each configured to convert a thermal drop across the thermoelectric elements into an electric potential by Seebeck effect. The thermoelectric generator includes a cavity between the substrate and the thermoelectric elements. The thermoelectric generator includes, within the cavity, a support structure for supporting the thermoelectric elements. The support structure has a thermal conductivity lower than a thermal conductivity of the substrate.

Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.

Abstract: An ultrasonic MEMS acoustic transducer formed in a body of semiconductor material having first and second surfaces opposite to one another. A first cavity extends in the body and delimits at the bottom a sensitive portion, which extends between the first cavity and the first surface of the body. The sensitive portion houses a second cavity and forms a membrane that extends between the second cavity and the first surface of the body. An elastic supporting structure extends between the sensitive portion and the body and is suspended over the first cavity.

Abstract: The present disclosure relates to solutions for operating a flyback converter comprising an active clamp. The flyback converter comprises two input terminals and two output terminals. A first electronic switch and the primary winding of a transformer are connected in series between the input terminals. An active clamp circuit is connected in parallel with the primary winding. The active clamp circuit comprises a series connection of a clamp capacitor and a second electronic switch. A third electronic switch and the secondary winding of the transformer are connected in series between the two output terminals. In particular, the present disclosure relates to solutions for switching the first, second and third electronic switch in order to achieve a zero-voltage switching of the first electronic switch.

Abstract: A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.

Abstract: In an embodiment a current limiting circuit includes a circuit configured to detect when an input or output current of a DC to DC converter exceeds or falls below a threshold and a controller configured to store a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold, store a second value representative of the level of the output voltage in response to the input or output current falling below a further threshold and modify a control signal based on the first and second values, wherein the control signal is modified based on the first and second values so that the control signal brings the output voltage to an intermediate voltage level between the level of the output voltage represented by the first value and the level of the output voltage represented by the second value.

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal imposes the drain-source current of the first transistor.

Abstract: A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.