Abstract: An integrated circuit includes a semiconductor substrate, electronic components integrated in the semiconductor substrate, an electric connection structure overlying the semiconductor substrate, and an conductive region, with elongated shaped, having a first and a second end. The conductive region is formed in the electric connection structure, extends over an entire length of the substrate and is not directly electrically connected to the electronic components. A first and a second synchronization connection element are electrically coupled to the first end and to the second end, respectively, of the conductive region and have each a respective synchronization connection portion facing the coupling face.

Abstract: The present disclosure is directed to micro-electromechanical system (MEMS) accelerometers that are configured for a user interface mode and a true wireless stereo (TWS) mode of an audio device. The accelerometers are fabricated with specific electromechanical parameters, such as mass, stiffness, active capacitance, and bonding pressure. As a result of the specific electromechanical parameters, the accelerometers have a resonance frequency, quality factor, sensitivity, and Brownian noise density that are suitable for both the user interface mode and the TWS mode.

Abstract: An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.

Abstract: In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.

Abstract: A microelectromechanical resonator device has: a main body, with a first surface and a second surface, opposite to one another along a vertical axis, and made of a first layer and a second layer, arranged on the first layer; a cap, having a respective first surface and a respective second surface, opposite to one another along the vertical axis, and coupled to the main body by bonding elements; and a piezoelectric resonator structure formed by: a mobile element, constituted by a resonator portion of the first layer, suspended in cantilever fashion with respect to an internal cavity provided in the second layer and moreover, on the opposite side, with respect to a housing cavity provided in the cap; a region of piezoelectric material, arranged on the mobile element on the first surface of the main body; and a top electrode, arranged on the region of piezoelectric material, the mobile element constituting a bottom electrode of the piezoelectric resonator structure.

Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.

Abstract: The present disclosure relates to a method implemented by a first NFC device, wherein the establishment of a transaction with a second NFC device configured in reader mode is performed when the signal level received by the first device, configured in card mode, reaches a first threshold, depending on the type of modulation technology of the second device.

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.

Abstract: First combinational, arithmetic, or combinational and arithmetic, operations are applied to data and an expected value, generating result bit sequences. When the value of the data corresponds to the expected value, the result bit sequences are different from each other and correspond to expected values of the result bit sequences. Second operations are applied a first memory address, a second memory address, and the result bit sequences, generating a memory address. When values of the generated result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address. When values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address. A software routine starting at the generated memory address is executed.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

Abstract: A circuit includes an electronic switch configured to be coupled intermediate a high-voltage node and low-voltage circuitry and configured to couple the low-voltage circuitry to the high-voltage node. A voltage-sensing node is configured to be coupled to the high-voltage node via a pull-up resistor. A further electronic switch can be switched to a conductive state to couple the voltage-sensing node and the control node of the electronic switch. A comparator compares a threshold with a voltage at the voltage-sensing node and causes the further electronic switch to switch on in response to the voltage at said voltage-sensing node reaching said threshold. A charge pump coupled to the current flow-path of the electronic switch is activated to the conductive state to pump electric charge from the current flow-path of the electronic switch to the control node of the electronic switch via the further electronic switch switched to the conductive state.

Abstract: A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.

Abstract: An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.

Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.

Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.

Abstract: An optoelectronic device includes a backlight panel illuminating a display panel. The backlight panel includes an array of light emitting pixels, with each light emitting pixel including at least one subpixel formed by one or more light emitting diodes positioned on a substrate. At least one photodetector is positioned on the substrate and arranged to detect an amount of reflected light emitted by said subpixel and reflected by the display panel.

Abstract: The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.