Abstract: Described herein is an electronic device, including a pixel and a turn-off circuit. The pixel includes a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage node and an anode selectively coupled to ground through an enable circuit, and a clamp diode having an anode coupled to the anode of the SPAD and a cathode coupled to a turn-off voltage node. The turn-off circuit includes a sense circuit coupled between the turn-off voltage node and ground and configured to generate a feedback voltage, and a regulation circuit configured to sink current from the turn-off voltage node to ground based upon the feedback voltage such that a voltage at the turn-off voltage node maintains generally constant.

Abstract: A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.

Abstract: In an embodiment a method for testing a digital electronic circuit includes coupling an external test equipment to a digital electronic circuit in order to apply an external voltage signal to the digital electronic circuit when an automatic test pattern generation (ATPG) procedure with a given test pattern is performed, wherein a value of the external voltage signal is controlled by the external test equipment and measuring, at the external test equipment, the digital supply voltage at an output of the voltage regulator and at an input of the internal digital circuitry, wherein the external voltage signal is applied to the differential inputs of the op-amp voltage regulator through an adaptation circuit to obtain determined values of the digital supply voltage.

Abstract: A method includes applying heat to a metal oxide sensing element of a gas sensor, varying the heat applied to the metal oxide sensing element for at least a time interval, and measuring an electrical resistance of the metal oxide sensing element versus variation of the heat for a time interval. The measurement of electrical resistance of the metal oxide sensing element versus variation of the heat applied to the metal oxide sensing element is compared to a set of corresponding reference measurements associated with a plurality of different target gases. A further sensor parameter versus the variation of electrical resistance and variation of the heat applied is measured to obtain a three-dimensional trajectory corresponding to variation of the sensor resistance, the variation of said heat and the variation of the further sensor parameter. This comparing includes comparing the trajectory in three dimensions to a set of reference three-dimensional objects.

Abstract: In accordance with an embodiment, a method includes: transmitting, by a first near-field communication (NFC) device, a field emission burst; comparing a characteristic property of a signal of the field emission burst to a detection threshold; determining a presence of a detection error based on the comparing; and adjusting the detection threshold based on a number of determined detection errors.

Abstract: An embodiment integrated circuit includes a first electromagnetic pulse detection device that comprises a first loop antenna formed in an interconnection structure of the integrated circuit, a first end of the first antenna being connected to a first node of application of a power supply potential and a second end of the antenna being coupled to a second node of application of the power supply potential, and a first circuit connected to the second end of the first antenna and configured to output a first signal representative of a comparison of a first current in the first antenna with a first threshold.

Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.

Abstract: A converter circuit converts an input signal applied across a first and a second input node into a converted output signal across a first and a second output node. The converter circuit includes a switching network coupled to the first input node via an inductor having a current flowing therethrough. In a hysteresis current control mode of the switching network, the current flowing through the inductor has a triangular waveform with rising and falling edges between a first current threshold and a second current threshold alternating with a switching frequency. The switching frequency is controlled by varying the distance between the first current threshold and the second current threshold.

Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.

Abstract: A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.

Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

Abstract: A control system for a laser scanning projector includes a mirror controller generating horizontal and vertical mirror synchronization signals for an oscillating mirror apparatus based upon a mirror clock signal, and laser modulation circuitry. The laser modulation circuitry generates horizontal and vertical laser synchronization signals as a function of a received laser clock signal, and generates control signals for a laser that emits a laser beam that impinges on the oscillating mirror apparatus. Synchronization circuitry generates the laser clock signal and sends the laser clock signal to the laser modulation circuitry, receives the horizontal and vertical mirror synchronization signals from the mirror controller, receives the horizontal and vertical laser synchronization signals from the laser modulation circuitry, and modifies the laser clock signal so as to achieve alignment between the horizontal and vertical mirror synchronization signals and the horizontal and vertical laser synchronization signals.

Abstract: A digital integrated circuit includes first areas of a substrate which incorporate digital functions and second areas of the substrate which are filler between first areas. A capacitance is provided by interdigitated metal-insulator-metal structures formed from a metallization level above the substrate. The structures of the capacitance are vertically aligned with one or more of the second areas.

Abstract: An apparatus includes a current mirror coupled to an output of an amplifier through control switches, a plurality of capacitors, each of which is coupled to a common node of a leg of the current mirror and a corresponding control switch, a first dipole coupled to a first input of an amplifier, a second dipole coupled to a second input of the amplifier, a third dipole coupled to an output of the apparatus configured to generate the bandgap reference voltage, and groups of switches coupled between the current mirror and the dipoles.

Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.

Abstract: A time-of-flight ranging system disclosed herein includes a receiver asserting a photon received signal in response to detection of light that has reflected off a target and returned to the time-of-flight ranging system. A first latch circuit has first and second data inputs receiving a first pair of differential timing references, the first latch circuit latching data values at its first and second data inputs to first and second data outputs based upon assertion of the photon received signal. A first counter counts latching events of the first latch circuit during which the first data output is asserted, and a second counter counts latching events of the first latch circuit during which the second data output is asserted. Processing circuitry determines distance to the target based upon counted latching events output from the first and second counters.

Abstract: A first electronic component, such as a sensor having opposed first and second surfaces and a first thickness, is arranged on a support member with the second surface facing towards the support member. A second electronic component, such as an integrated circuit mounted on a substrate and having a second thickness less than the first thickness, is arranged on the support member with a substrate surface opposed the second electronic component facing towards the support member. A package molding material is molded onto the support member to encapsulate the second electronic component while leaving exposed the first surface of the first electronic component. The support member is then removed to expose the second surface of the first electronic component and the substrate surface of the substrate.

Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.

Abstract: A semiconductor chip is arranged on a region of laser direct structuring (LDS) material of a laminar substrate. The semiconductor chip has a front active area facing towards, and a metallized back surface facing away from, the laminar substrate. An encapsulation of LDS material on the laminar substrate encapsulates the semiconductor chip with the metallized back surface of the semiconductor chip exposed at an outer surface of the encapsulation of LDS material. Electrically conductive lines and first vias are structured in the region of LDS material to electrically connect to the front active area of the semiconductor chip. A thermally conductive layer is plated over the outer surface of the encapsulation of LDS material in contact with the metallized back surface of the semiconductor chip. A heat extractor body of thermally conductive material is coupled in heat transfer relationship with the thermally conductive layer.

Abstract: A circuit includes two input nodes and two output nodes. A rectifier bridge is coupled to the input and output nodes. The rectifier bridge includes a first and second thyristors and a third thyristor coupled in series with a resistor in series. The series coupled third thyristor and resistor are coupled in parallel with one of the first and second thyristors. The first and second thyristors are controlled off, with the third thyristor controlled on, during start up with resistor functioning as an in in-rush current limiter circuit. In normal rectifying operation mode, the first and second thyristors are controlled on, with the third thyristor controlled off.