Patents Assigned to STMicroelectronics, Inc.
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Publication number: 20250151395Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.Type: ApplicationFiled: December 16, 2024Publication date: May 8, 2025Applicant: STMicroelectronics, Inc.Inventor: John H. ZHANG
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Publication number: 20250126850Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.Type: ApplicationFiled: December 23, 2024Publication date: April 17, 2025Applicant: STMicroelectronics, Inc.Inventors: Nicolas LOUBET, Pierre MORIN
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Patent number: 12224251Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.Type: GrantFiled: December 6, 2023Date of Patent: February 11, 2025Assignee: STMicroelectronics, Inc.Inventor: Ian Harvey Arellano
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Patent number: 12211772Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.Type: GrantFiled: March 7, 2022Date of Patent: January 28, 2025Assignees: STMicroelectronics S.r.l., STMicroelectronics, Inc.Inventors: Fulvio Vittorio Fontana, Davide Maria Benelli, Jefferson Sismundo Talledo
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Patent number: 12170240Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.Type: GrantFiled: April 19, 2023Date of Patent: December 17, 2024Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Maiden Grace Maming, Jefferson Sismundo Talledo
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Patent number: 12159820Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: GrantFiled: December 31, 2020Date of Patent: December 3, 2024Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
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Patent number: 12143719Abstract: A method includes dividing a field of view into a plurality of zones and sampling the field of view to generate a photon count for each zone of the plurality of zones, identifying a focal sector of the field of view and analyzing each zone to select a final focal object from a first prospective focal object and a second prospective focal object.Type: GrantFiled: September 20, 2023Date of Patent: November 12, 2024Assignees: STMicroelectronics France, STMicroelectronics, Inc., STMicroelectronics (Research & Development) LimitedInventors: Darin K. Winterton, Donald Baxter, Andrew Hodgson, Gordon Lunn, Olivier Pothier, Kalyan-Kumar Vadlamudi-Reddy
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Patent number: 12111158Abstract: A microelectromechanical system (MEMS) gyroscope includes a driving mass and a driving circuit that operates to drive the driving mass in a mechanical oscillation at a resonant drive frequency. An oscillator generates a system clock that is independent of and asynchronous to the resonant drive frequency. A clock generator circuit outputs a first clock and a second clock that are derived from the system clock. The drive loop of the driving circuit including an analog-to-digital converter (ADC) circuit that is clocked by the first clock and a digital signal processing (DSP) circuit that is clocked by the second clock.Type: GrantFiled: April 18, 2023Date of Patent: October 8, 2024Assignee: STMicroelectronics, Inc.Inventors: Deyou Fang, Chao-Ming Tsai, Milad Alwardi, Yamu Hu, David McClure
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Patent number: 12092653Abstract: In one embodiment, a method for detecting functional state of a microelectromechanical (MEMS) sensor is described. The method includes monitoring an input common-mode feedback (ICMFB) voltage generated by an ICMFB circuit coupled to the MEMS sensor through a plurality of nodes. The method also includes determining, using the monitored ICMFB voltage, whether all of the plurality of nodes of the MEMS sensor are electrically connected to the ICMFB circuit.Type: GrantFiled: September 10, 2021Date of Patent: September 17, 2024Assignee: STMicroelectronics, Inc.Inventors: Davy Choi, Yamu Hu, Deyou Fang
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Patent number: 12094725Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.Type: GrantFiled: December 9, 2021Date of Patent: September 17, 2024Assignee: STMicroelectronics, Inc.Inventors: Jefferson Talledo, Frederick Ray Gomez
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Patent number: 12080657Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.Type: GrantFiled: February 13, 2023Date of Patent: September 3, 2024Assignee: STMicroelectronics, Inc.Inventor: Jefferson Sismundo Talledo
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Patent number: 12074100Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.Type: GrantFiled: December 22, 2020Date of Patent: August 27, 2024Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
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Patent number: 12066881Abstract: A method for operating an electronic device includes while a display is in low power mode, detecting based on data collected by a time of flight (ToF) sensor, a movable object within a field of view of the electronic device; in response to the detecting initiating a period of detection having a plurality of frames, the period of detection being a time period over which a distance value indicative of a distance between the movable object and the display is detected; for each of the plurality of frames, changing the distance value to reflect whether the movable object is moving near or further from the electronic device; detecting that the distance value after the period of detection is less than a threshold distance value indicative of the movable object approaching the display; if the distance value is less than the threshold distance value, waking up the display.Type: GrantFiled: June 14, 2022Date of Patent: August 20, 2024Assignees: STMICROELETRONICS (BEIJING) R&D CO., LTD., STMicroelectronics (Grenoble 2) SAS, STMicroelectronics, Inc.Inventors: Arnaud Deleule, Kalyan-Kumar Vadlamudi-Reddy, Darin K Winterton, Jihong Chen, Olivier Lemarchand
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Publication number: 20240162168Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.Type: ApplicationFiled: December 6, 2023Publication date: May 16, 2024Applicant: STMicroelectronics, Inc.Inventor: Ian Harvey ARELLANO
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Publication number: 20240124300Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: STMicroelectronics, Inc.Inventor: Jefferson Sismundo TALLEDO
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Publication number: 20240113064Abstract: An electronic device includes an integrated circuit (IC) with its second face bonded to a first surface of a first support. A conductive clip has a first portion that is elongate and extends across the IC, having its second surface bonded to a first face of the IC by a solder layer. A second portion of the clip extends from the first portion away from the IC toward a second support with the second surface bonded to a first surface of the second support. A first surface of the clip has a pattern formed therein including a depressed floor with fins extending upwardly therefrom. Through-holes extend through the depressed floor to the second surface of the clip. An encapsulating layer covers portions of the first and second supports, IC, and clip while leaving the first surface of the first portion exposed to permit heat to radiate away therefrom.Type: ApplicationFiled: August 11, 2023Publication date: April 4, 2024Applicant: STMicroelectronics, Inc.Inventor: Jefferson Sismundo TALLEDO
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Patent number: 11927443Abstract: A microelectromechanical device is provided. A vibrating structure gyroscope included in the device employs a temporal differential sensing method alone or a spatial differential sensing method in combination with the temporal differential sensing method. When used in combination, the temporal sensing method may be applied before the spatial sensing method or applied after the spatial sensing method. The temporal differential sensing samples signals at times t1 and t2 when velocity of a sensing mass within the vibrating structure gyroscope is maximum and has an opposite sign. The temporal sensing method improves Euler and Centrifugal forces cancellation and increases the signal to noise ratio if forces remain equal at times t1 and t2. Applying a high sampling speed can result in times t1 and t2 being sufficiently close to each other and therefore cancel any error terms associated with Euler and Centrifugal forces.Type: GrantFiled: August 4, 2022Date of Patent: March 12, 2024Assignee: STMicroelectronics, Inc.Inventor: Andrea Lorenzo Vitali
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Patent number: 11916090Abstract: A first side of a tapeless leadframe package is etched to form a ring shaped protrusion and a lead protrusion extending from a base layer. An integrated circuit die is mounted to tapeless leadframe package in flip chip orientation with a front side facing the first side. An electrical and mechanical attachment is made between a bonding pad of the integrated circuit die and the lead protrusion. A mechanical attachment is made between the front side of the integrated circuit die and the ring shaped protrusion. The integrated circuit die and the protrusions from the tapeless leadframe package are encapsulated within an encapsulating block. The second side of the tapeless leadframe package is then etched to remove portions of the base layer and define a lead for a leadframe from the lead protrusion and further define a die support for the leadframe from the ring shaped protrusion.Type: GrantFiled: June 9, 2021Date of Patent: February 27, 2024Assignee: STMicroelectronics, Inc.Inventors: Aaron Cadag, Rohn Kenneth Serapio, Ela Mia Cadag
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Patent number: 11897763Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.Type: GrantFiled: November 24, 2020Date of Patent: February 13, 2024Assignee: STMicroelectronics, Inc.Inventor: Jefferson Sismundo Talledo
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Patent number: 11862579Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.Type: GrantFiled: June 21, 2022Date of Patent: January 2, 2024Assignee: STMicroelectronics, Inc.Inventor: Ian Harvey Arellano