Patents Assigned to STMicroelectronics, Inc.
-
Patent number: 11613918Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.Type: GrantFiled: April 4, 2019Date of Patent: March 28, 2023Assignees: STMicroelectronics S.r.l., STMicroelectronics, Inc.Inventors: Williamson Sy, Emiliano Mario Piccinelli, Keith Walters
-
Patent number: 11610851Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.Type: GrantFiled: April 2, 2021Date of Patent: March 21, 2023Assignee: STMICROELECTRONICS, INC.Inventor: Jefferson Sismundo Talledo
-
Publication number: 20230068273Abstract: The present disclosure is directed to semiconductor packages manufactured utilizing a leadframe with varying thicknesses. The leadframe with varying thicknesses has a reduced likelihood of deformation while being handled during the manufacturing of the semiconductor packages as well as when being handled during a shipping process. The method of manufacturing is not required to utilize a leadframe tape based on the leadframe with varying thicknesses. This reduces the overall manufacturing costs of the semiconductor packages due to the reduced materials and steps in manufacturing the semiconductor packages as compared to a method that utilizes a leadframe tape to support a leadframe. The semiconductor packages may include leads of varying thicknesses formed by utilizing the leadframe of varying thicknesses to manufacture the semiconductor packages.Type: ApplicationFiled: August 16, 2022Publication date: March 2, 2023Applicant: STMICROELECTRONICS, INC.Inventor: Jefferson Sismundo TALLEDO
-
Patent number: 11579710Abstract: Digital signal processing circuitry, in operation, determines, based on accelerometer data, a carry-position of a device. Double-tap detection parameters are set using the determined carry-position. Double-taps are detected using the set double-tap detection parameters. In response to detection of a double-tap, control signals, such as a flag or an interrupt signal, are generated and used to control operation of the device. For example, a device may enter a wake mode of operation in response to detection of a double-tap.Type: GrantFiled: December 15, 2020Date of Patent: February 14, 2023Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS, INC.Inventors: Stefano Paolo Rivolta, Mahaveer Jain, Ashish Bhargava
-
Patent number: 11573303Abstract: Disclosed herein is a system for detecting rotational speed and early failures of an electronic device. The system includes a rotating disk affixed to a rotating shaft of the electronic device. The rotating disk has projections extending from its periphery. A time of flight ranging system determines distance to the projections extending from the rotating disk. Processing circuitry determines a rotational speed of the rotating shaft from the determined distances to the projections extending from the rotating disk, and detects whether the electronic device is undergoing an early failure from the determined distances to the projections extending from the rotating disk. Rotational speed is determined from the time between successive peaks in the determined distances, and early failures (for example, due to wobble of the shaft) are determined where the peaks vary unexpectedly in magnitude.Type: GrantFiled: December 18, 2019Date of Patent: February 7, 2023Assignee: STMicroelectronics, Inc.Inventors: Cheng Peng, Xiaoyong Yang
-
Publication number: 20230036201Abstract: A semiconductor package device having a porous copper adhesion promoter layer is provided. The porous copper adhesion promoter layer developed via de-metallization of the intermetallic compound layer grown after the thermal treatment of a thin metal layer plated on the copper base material. The highly selective de-metallization of the intermetallic compound layer ensures that the plated surfaces are not affected and does not create wire-bondability issues. The porous copper layer solves the delamination between the carrier and the epoxy molding compound by providing mechanical interlock features. Further, increasing the surface area of contact between the carrier and the epoxy molding compound improves the mechanical interlock features.Type: ApplicationFiled: July 11, 2022Publication date: February 2, 2023Applicant: STMICROELECTRONICS, INC.Inventor: Ian Harvey Juralbal ARELLANO
-
Publication number: 20230032490Abstract: A robotic device including one or more proximity sensing systems coupled to various portions of a robot body. The proximity sensing systems detect a distance of an object about the robot body and the robotic device reacts based on the detected distance. The proximity sensing systems obtain a three-dimensional (3D) profile of the object to determine a category of the object. The distance of the object is detected multiple times in a sequence to determine a movement path of the object.Type: ApplicationFiled: August 9, 2022Publication date: February 2, 2023Applicant: STMICROELECTRONICS, INC.Inventors: Cheng PENG, Xiaoyong YANG
-
Patent number: 11569384Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.Type: GrantFiled: October 19, 2020Date of Patent: January 31, 2023Assignee: STMICROELECTRONICS, INC.Inventors: Nicolas Loubet, Pierre Morin
-
Publication number: 20230018529Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.Type: ApplicationFiled: September 20, 2022Publication date: January 19, 2023Applicant: STMICROELECTRONICS, INC.Inventor: John H. ZHANG
-
Patent number: 11557548Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.Type: GrantFiled: December 29, 2020Date of Patent: January 17, 2023Assignee: STMicroelectronics, Inc.Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
-
Patent number: 11552007Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.Type: GrantFiled: February 25, 2021Date of Patent: January 10, 2023Assignee: STMicroelectronics, Inc.Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
-
Patent number: 11550531Abstract: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.Type: GrantFiled: July 20, 2021Date of Patent: January 10, 2023Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Benedetto Vigna, Mahesh Chowdhary, Matteo Dameno
-
Publication number: 20230006823Abstract: A secure element device that is configured to be cryptographically bound to a host device includes a secure element host key slot configured to store host key information that allows only the host device to control the secure element, a secure memory storing binding information, and limited functionality allowing the binding information to be read from the secure memory by the host device during a binding process. The binding information is cryptographically correlated with the host key information. The host key information is generated by the host device using the binding information read from the secure element and a secret key. The secure element device further includes general functionality only accessible to the host device using the host key information that is generated by the host device. The secure memory includes prevention measures impeding unauthorized entities from obtaining information from the secure memory.Type: ApplicationFiled: September 7, 2022Publication date: January 5, 2023Applicant: STMicroelectronics, Inc.Inventor: Giuseppe Pilozzi
-
Patent number: 11542152Abstract: A cavity type semiconductor package with a substrate and a cap is disclosed. The semiconductor package includes a first semiconductor die coupled to the substrate and a layer of flexible material on a surface of the cap. A trace is on the layer of flexible material. The cap is coupled to the substrate with the layer of flexible material and the trace between the cap and the substrate. A second semiconductor die is coupled to the layer of flexible material and the trace on the cap. The cap further includes an aperture to expose the second semiconductor die to the ambient environment. The layer of flexible material absorbs stress during operation cycles of the package induced by the different coefficient of thermal expansions of the cap and the substrate to reduce the likelihood of separation of the cap from the substrate.Type: GrantFiled: July 21, 2020Date of Patent: January 3, 2023Assignee: STMicroelectronics, Inc.Inventor: Jefferson Talledo
-
Patent number: 11528407Abstract: A method includes dividing a field of view into a plurality of zones and sampling the field of view to generate a photon count for each zone of the plurality of zones, identifying a focal sector of the field of view and analyzing each zone to select a final focal object from a first prospective focal object and a second prospective focal object.Type: GrantFiled: December 15, 2020Date of Patent: December 13, 2022Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS, INC., STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventors: Darin K. Winterton, Donald Baxter, Andrew Hodgson, Gordon Lunn, Olivier Pothier, Kalyan-Kumar Vadlamudi-Reddy
-
Patent number: 11515418Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.Type: GrantFiled: May 28, 2020Date of Patent: November 29, 2022Assignee: STMICROELECTRONICS, INC.Inventors: Qing Liu, John H. Zhang
-
Patent number: 11507654Abstract: A secure engine method includes providing an embedded microcontroller in an embedded device, the embedded microcontroller having internal memory. The method also includes providing a secure environment in the internal memory. The secure environment method recognizes a boot sequence and restricts user-level access to the secure environment by taking control over the secure environment memory. Taking such control may include disabling DMA controllers, configuring at least one memory controller for access to the secure environment, preventing the execution of instructions fetched from outside the secure environment, and only permitting execution of instructions fetched from within the secure environment. Secure engine program instructions are then executed to disable interrupts, perform at least one secure operation, and re-enable interrupts after performing the at least one secure operation.Type: GrantFiled: August 14, 2020Date of Patent: November 22, 2022Assignee: STMICROELECTRONICS, INC.Inventors: Maurizio Gentili, Massimo Panzica
-
Patent number: 11502388Abstract: An embodiment electronic device includes a ground plane; and an antenna. The antenna includes a first trace having a first end and a second end, the second end of the first trace being electrically coupled to the ground plane. The antenna also includes a second trace distinct and physically separated from the first trace, the second trace having a first end and a second end, the second end of the second trace being electrically coupled to the ground plane, the first trace and the second trace forming discontinuous portions of the antenna.Type: GrantFiled: January 21, 2019Date of Patent: November 15, 2022Assignee: STMICROELECTRONICS, INC.Inventors: Pierre Rizzo, John Coronado, Mohammad Mazooji
-
Publication number: 20220358062Abstract: A microcontroller includes a memory, direct memory access (DMA) controllers and a microprocessor. The microprocessor maintains one or more memory protection (MP) configurations to control access to protected memory areas of the microcontroller. In response to a secure service call of an unsecure user-application, the microprocessor executes a state machine which disables interrupt requests, determining whether DMA controller configurations and MP configurations satisfy secure-service criteria. When the secure-service criteria are satisfied, at least one secure operation associated with the secure service call is performed, and memory areas accessed during the execution of the at least one secure operation are cleaned. The interrupt requests are re-enabled and a response to the secure service call is generated.Type: ApplicationFiled: May 4, 2021Publication date: November 10, 2022Applicant: STMICROELECTRONICS, INC.Inventors: Massimo PANZICA, Maurizio GENTILI
-
Patent number: 11495676Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.Type: GrantFiled: August 7, 2020Date of Patent: November 8, 2022Assignee: STMICROELECTRONICS, INC.Inventor: John H. Zhang