Patents Assigned to STMicroelectronics, Inc.
  • Patent number: 11658098
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Publication number: 20230128205
    Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal having a variably controlled excitation voltage and a fixed pulse width is applied to the sensing capacitor. The leading and trailing edges of the test signal are aligned to coincide with reset phases of a sensing circuit coupled to the sensing capacitor. The variably controlled excitation voltage of the test signal is configured to cause an electrostatic force which produces a desired physical displacement of the mobile mass. During a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the actual physical displacement of the mobile mass is sensed for comparison to the desired physical displacement.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Applicants: STMicroelectronics S.r.l., STMicroelectronics, Inc.
    Inventors: Marco GARBARINO, Davy CHOI, Francesco RIZZINI, Yamu HU
  • Patent number: 11613918
    Abstract: A method and device for unlatching a door from a frame, using a keyless door latch system, is provided. In one embodiment, a secondary unlocking component receives a signal and derives power from the signal to provide a power source for the keyless door latch system. A microcontroller generates a control signal and an actuator, in response to receiving the control signal, actuates the secondary unlocking component, which allows an energy source, from an exterior of the door, to be transferred to the keyless door latch system for the unlatching of the door.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: March 28, 2023
    Assignees: STMicroelectronics S.r.l., STMicroelectronics, Inc.
    Inventors: Williamson Sy, Emiliano Mario Piccinelli, Keith Walters
  • Patent number: 11573303
    Abstract: Disclosed herein is a system for detecting rotational speed and early failures of an electronic device. The system includes a rotating disk affixed to a rotating shaft of the electronic device. The rotating disk has projections extending from its periphery. A time of flight ranging system determines distance to the projections extending from the rotating disk. Processing circuitry determines a rotational speed of the rotating shaft from the determined distances to the projections extending from the rotating disk, and detects whether the electronic device is undergoing an early failure from the determined distances to the projections extending from the rotating disk. Rotational speed is determined from the time between successive peaks in the determined distances, and early failures (for example, due to wobble of the shaft) are determined where the peaks vary unexpectedly in magnitude.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 7, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Cheng Peng, Xiaoyong Yang
  • Patent number: 11557548
    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 17, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Lester Joseph Belalo, Ela Mia Cadag
  • Patent number: 11552007
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20230006823
    Abstract: A secure element device that is configured to be cryptographically bound to a host device includes a secure element host key slot configured to store host key information that allows only the host device to control the secure element, a secure memory storing binding information, and limited functionality allowing the binding information to be read from the secure memory by the host device during a binding process. The binding information is cryptographically correlated with the host key information. The host key information is generated by the host device using the binding information read from the secure element and a secret key. The secure element device further includes general functionality only accessible to the host device using the host key information that is generated by the host device. The secure memory includes prevention measures impeding unauthorized entities from obtaining information from the secure memory.
    Type: Application
    Filed: September 7, 2022
    Publication date: January 5, 2023
    Applicant: STMicroelectronics, Inc.
    Inventor: Giuseppe Pilozzi
  • Patent number: 11542152
    Abstract: A cavity type semiconductor package with a substrate and a cap is disclosed. The semiconductor package includes a first semiconductor die coupled to the substrate and a layer of flexible material on a surface of the cap. A trace is on the layer of flexible material. The cap is coupled to the substrate with the layer of flexible material and the trace between the cap and the substrate. A second semiconductor die is coupled to the layer of flexible material and the trace on the cap. The cap further includes an aperture to expose the second semiconductor die to the ambient environment. The layer of flexible material absorbs stress during operation cycles of the package induced by the different coefficient of thermal expansions of the cap and the substrate to reduce the likelihood of separation of the cap from the substrate.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 3, 2023
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Talledo
  • Publication number: 20220293498
    Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 15, 2022
    Applicants: STMicroelectronics S.r.l., STMicroelectronics, Inc.
    Inventors: Fulvio Vittorio FONTANA, Davide Maria BENELLI, Jefferson Sismundo TALLEDO
  • Patent number: 11393774
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 19, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Patent number: 11394195
    Abstract: A power supply interface includes a first switch that couples an input terminal to an output terminal. A voltage dividing bridge is coupled to receive a supply potential. A comparator has a first input connected to a first node of the bridge and a second input configured to receive a constant potential. A digital-to-analog converter generates a control voltage that is selectively coupled by a second switch to a second node of the bridge. A circuit control controls actuation of the second switch based on operating mode and generates a digital value input to the converter based on a negotiated set point of the supply potential applied to the input terminal.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: July 19, 2022
    Assignees: STMicroelectronics (Tours) SAS, STMicroelectronics, Inc.
    Inventors: Mathieu Rouviere, Jeffrey Blauser, Jr., Karl Grange, Mohamed Saadna
  • Publication number: 20220206085
    Abstract: An electronic device includes a magnetometer that outputs magnetometer sensor signals and a gyroscope that outputs gyroscope sensor signals. The electronic device includes a magnetometer calibration module that calibrates the magnetometer utilizing the gyroscope sensor signals. The electronic device generates a first magnetometer calibration parameter based on a Kalman filter process. The electronic device generates a second magnetometer calibration parameter based on a least squares estimation process.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Mahaveer JAIN, Mahesh CHOWDHARY
  • Patent number: 11373322
    Abstract: The present disclosure provides a device and method for depth sensing by utilizing the combination of a ranging sensor and an image sensor. The ranging sensor can accurately detect distance measurement from an object. The image sensor can take images with high resolution of the object. By combining each sensor data from the ranging sensor and the image sensor, accurate depth information with high resolution of the object may be obtained. A structured light having patterned shapes are used in conjunction with the ranging sensor to receive reflected patterned shapes of the object. These reflected patterned shapes are used to analyze distance measurements associated with the specific patterned shapes. These distance measurements from both the ranging sensor and the image sensor is aligned and combined to generate an accurate depth map with high resolution using a processor of an electronic device including the ranging sensor and the image sensor.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 28, 2022
    Assignee: STMicroelectronics, Inc.
    Inventors: Xiaoyong Yang, Chang Myung Ryu, James Kath, Rui Xiao
  • Patent number: 11348863
    Abstract: In various embodiments, the present disclosure provides semiconductor packages, devices, and methods. In one embodiment, a device includes a die pad, leads that are spaced apart from the die pad, and a semiconductor die on the die pad. The semiconductor die has a first surface and a second surface opposite the first surface. The second surface faces the die pad. An encapsulant is provided on the semiconductor die, the die pad and the leads, and the encapsulant has a first surface opposite the die pad and the leads, and a second surface opposite the first surface. The second surface of the encapsulant extends between the die pad and an adjacent lead. The second surface of the encapsulant is spaced apart from the first surface of the encapsulant by a first distance, and an exposed surface of the die pad is spaced apart from the first surface of the encapsulant by a second distance that is greater than the first distance.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 31, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Jefferson Talledo
  • Patent number: 11320452
    Abstract: A microelectromechanical system (MEMS) accelerometer sensor has a mobile mass and a sensing capacitor. To self-test the sensor, a test signal is applied to the sensing capacitor during a reset phase of a sensing circuit coupled to the sensing capacitor. The test signal is configured to cause an electrostatic force which produces a physical displacement of the mobile mass corresponding to a desired acceleration value. Then, during a read phase of the sensing circuit, a variation in capacitance of sensing capacitor due to the physical displacement of the mobile mass is sensed. This sensed variation in capacitance is converted to a sensed acceleration value. A comparison of the sensed acceleration value to the desired acceleration value provides an indication of an error in operation of the MEMS accelerometer sensor if the sensed acceleration value and desired acceleration value are not substantially equal.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 3, 2022
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.r.l.
    Inventors: Yamu Hu, David McClure, Alessandro Tocchio, Naren K. Sahoo, Anthony Junior Casillan
  • Publication number: 20220128360
    Abstract: A microelectromechanical system (MEMS) gyroscope sensor has a sensing mass and a quadrature error compensation control loop for applying a force to the sensing mass to cancel quadrature error. To detect fault, the quadrature error compensation control loop is opened and an additional force is applied to produce a physical displacement of the sensing mass. A quadrature error resulting from the physical displacement of the sensing mass in response to the applied additional force is sensed. The sensed quadrature error is compared to an expected value corresponding to the applied additional force and a fault alert is generated if the comparison is not satisfied.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Yamu HU, Deyou FANG, David MCCLURE, Huantong ZHANG, Naren K. SAHOO
  • Patent number: 11308979
    Abstract: A method and apparatus for classifying a spatial environment as open or enclosed are provided. In the method and apparatus, one or more microphones detect ambient sound in a spatial environment and output an audio signal representative of the ambient sound. A processor determines a spatial environment impulse response (SEIR) for the audio signal and extracts one or more features of the SEIR. The processor classifies the spatial environment as open or enclosed based on the one or more features of the SEIR.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: April 19, 2022
    Assignees: STMicroelectronics, Inc., STMicroelectronics International N.V.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Rajendar Bahl
  • Patent number: 11303859
    Abstract: An image projection device, such as a pico projector or LCD projector, includes image projection circuitry configured to generate a light beam having a power. The image projection circuitry projects the light beam onto and focuses the light beam on a projection surface located an imaging distance from the image projection circuitry. A time-of-flight sensor is configured to sense the imaging distance between the image projection circuitry and the projection surface and to generate an imaging distance signal indicating the sensed imaging distance. Control circuitry is coupled to the image projection circuitry and to the time-of-flight sensor and is configured to adjust the power and the focus of the light beam based upon the imaging distance signal.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 12, 2022
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics, Inc.
    Inventors: Neale Dutton, Xiaoyong Yang, Kevin Channon
  • Publication number: 20220102166
    Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.
    Type: Application
    Filed: December 9, 2021
    Publication date: March 31, 2022
    Applicant: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Frederick Ray Gomez
  • Patent number: 11264286
    Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 1, 2022
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin, Yann Mignot