Abstract: A static random access memory cell comprising a storage latch having a first upper power supply voltage connection to a first bit line, a second upper power supply voltage connection to a second bit line, and a connection to a lower power supply voltage. A first access circuit connects the storage latch to the first bit line and a second access circuit connects the storage latch to the second bit line, wherein the storage latch is accessed utilizing the first access circuit and the second access circuit.

Abstract: The bond between a flip chip integrated circuit and a substrate is subject to mechanical stress from thermal cycles. This problem is exaggerated when the substrate has a rate of thermal expansion which is appreciably different from that of silicon. This problem is further exaggerated when the IC has a large footprint because it will experience a larger absolute expansion. A solution is proposed to this problem which involves creating an anchoring point. The anchoring point can be in either the IC or the substrate and can be a through-hole or a surface indentation such as a groove or a cutout. The anchoring point is filled with the underfill material during the underfill process. The anchoring point thus provides additional mechanical strength to the bond between the IC and the substrate.

Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome.

Abstract: A semiconductor device structure and method are presented for increasing a breakdown voltage of a junction between a substrate of first conductivity type and a device region. The structure includes a region of second conductivity type in the substrate completely buried in the substrate below and separated from the device region. The region of second conductivity type is located a predetermined distance away from the device region. The distance is sufficient to permit a depletion region to form between the region of second conductivity type and the device region, when a first voltage is applied between the device region and the substrate. The distance also is determined to produce a radius of curvature of the depletion region, when a second voltage that is larger than the first voltage is applied between the device region and the substrate, that is larger than a radius of curvature of the depletion region about the device region that would be formed if the region of second conductivity type were not present.

Abstract: A method is provided for improving the adhesion between a photoresist layer and a dielectric, and an integrated circuit formed according to the same. A conformal dielectric layer is formed over the integrated circuit. An interlevel dielectric layer is formed over the conformal dielectric layer. The interlevel dielectric layer is doped such that the doping concentration allows the layer to reflow while partially inhibiting the adhesion of the doped layer to photoresist at an upper surface of the doped layer. An undoped dielectric layer is formed over the doped dielectric layer. A photoresist layer is formed and patterned over the undoped dielectric layer which adheres to the undoped dielectric layer. The undoped dielectric, the interlevel dielectric and the conformal dielectric layers are etched to form an opening exposing a portion of an underlying conductive region.

Abstract: A short circuit protection circuit which has a first short circuit protection circuit in parallel with a second short circuit protection circuit is disclosed. The first short circuit protection circuit includes a sense resistor and a comparator for detecting the short circuit, and a transistor and current source for turning off the low side driver when the short circuit is detected. The second short circuit protection circuit includes a current mirror, zener diode, transistor, and current source connected in series. The second short circuit protection circuit is in parallel with the first short circuit protection circuit. The second short circuit protection circuit accelerates the turn-off of the low-side driver with out affecting the stability of the circuit.

Abstract: An electronic speed limit notification system comprises a transmitter for transmitting speed limit information ("SLI"), and a receiver for receiving said transmitted SLI, wherein said receiver can be physically located in a vehicle. The SLI comprises one or more speed limits, wherein each speed limit is the maximum or minimum legal speed for specific vehicles on a specific segment of a specific road traveling in a specific direction.

Abstract: A power down brake latch circuit for dynamically braking a spindle motor in a disk drive system is disclosed. The power down brake latch circuit includes a reservoir capacitor, a smoothing capacitor, a timing circuit, and a logic circuit. The timing circuit includes a voltage divider and a bandgap comparator. The smoothing capacitor absorbs a BEMF voltage from the spindle motor as it rotates after losing power. The timing circuit generates a first signal when a voltage on the smoothing capacitor falls below a threshold. The logic circuit brakes the spindle motor in response to the loss of power and the generation of the first signal.

Abstract: A non-volatile storage device storing a data bit received from a bitline via an accessing circuit. A coupling circuit couples either the bitline, or a complementary bitline to a biasing circuit dependent on the logic level of the data bit stored in the storage device. The biasing circuit generates a match signal when a data bit having the same logic level as the stored data bit is applied to the bitline.

Abstract: A layout is provided for an SRAM structure. The layout includes a first storage transistor cross-coupled to a second storage transistor to form an SRAM cell. The source regions of the first and second storage transistors are formed in a common region in the substrate to provide a more compact and dense array. The memory cell also includes a first access transistor and a second access transistor appropriately coupled to the appropriate data storage notes. The gate electrodes for the storage transistors and the access transistors are substantially parallel to each other thus providing advantages in operational characteristics and layout efficiencies. The channel regions are also exactly perpendicular to the gate electrodes and are parallel to each other for each of their respective transistors, thereby obtaining similar benefits. The memory cell is designed having a low aspect ratio, preferably lower than 1.2.

Abstract: A dynamic access memory (DRAM) device includes a plurality of memory cells for storing data signals. The DRAM device has a row decoding mechanism that allows selected memory cells to be accessed upon receipt of a row address signal during a read operation and a write operation. A latching mechanism is provided and receives and holds onto the data signals from the selected memory cells when activated during the read operation and also isolates itself from the selected memory cells when deactivated during the write operation. An included refresh address generating mechanism generates a plurality of internal row address signals that allows selection of a plurality of memory cells for refreshing the stored data signals. The DRAM device also has a multiplexer mechanism that transmits a plurality of external row address signals to the row decoding mechanism in the write operation.

Abstract: A circuit and method for varying the time of a write cycle. A variable timer circuit is provided coupled to a write simulation circuit. The write simulation circuit receives a signal from a start write sensing circuit indicating that data is being written to memory cells of the array. The write simulation circuit includes a memory cell replicate which replicates the time required for writing data to memory cells of the array. After the memory cell replicate has changed state, a signal is output via a switching circuit to the variable timer circuit for generation of a write termination signal. The memory cells are tested at various write cycle speeds by controlling the variable timer circuit. The variable timer circuit is set to terminate the write as quickly as possible after a successful write to the memory cells has been completed.

Abstract: A catalytic converter of an engine, such as might be found in an automotive engine system, is capable of being quickly and electrically heated in order to reduce pollution emissions during critical cold start conditions. During cold start conditions, i.e. upon starting the engine, for a predetermined period of time the catalytic converter directly receives electrical power via a quick heating path connecting a catalyst power switch to the catalytic converter. Following the predetermined period of time after which the catalytic converter has been electrically heated, the catalyst power switch is connected to a junction block, such as a starter motor assembly, of the automotive engine system via a normal path.

Abstract: A modular integrated circuit package is mounted on a surface of a printed circuit board. The integrated circuit package includes a rigid interposer releasably coupling a component module to a substrate member designed to be affixed to the printed circuit board. The substrate member has a first side with plural first electrical connectors for connection to the circuit board and a second side with second electrical connectors coupled to the first electrical connectors. The interposer includes a plurality of electrical connectors that couple electrical connectors of the component module to the second electrical connectors of the substrate member. The component module also includes plural clip members that engage a lower surface of the interposer to releasably couple the component module to the interposer.

Abstract: The pulse width of an internal edge transition detection signal of a memory device is selectably varied by varying the logic state of one or more control signals of the memory device. A number of edge transition detection signals generated by input buffers of the memory device are wire-configured together, such as by a wired-NOR or a wired-NAND configuration, to generate one or more edge transition detection busses. The one or more edge transition detection busses, together with two or more control signals, are introduced to an edge transition detection driver that determines the logic state of a device edge transition detection signal that is generated for use by the entire memory device. Changing the combination of logic states of the control signals allows the pulse width of the device edge transition detection signal to be selectably varied.

Abstract: A read circuit reads data stored in a memory cell that is coupled to a bit line. The read circuit includes a comparison circuit, such as a sense amplifier, having a first input terminal coupled to the bit line and having a second input terminal and a data output terminal. A switch is coupled between the bit line and the second input terminal of the comparison circuit and includes a control terminal that is coupled to receive a control signal.

Abstract: A clock generator or oscillator circuit for use in an integrated circuit for generating a clock signal includes a 555 timer circuit. The time constant circuit of the 555 timer includes a heater element for generating heat and a transducer for converting heat generated by the heater element into electrical energy. The clock signal is generated in response to the heating and cooling of the heater element.

Abstract: A method and a circuit for switching a motor controller from pulse width modulation to linear control for a brush-less, sensor-less, poly-phase DC motor. The method includes steps of operating a drive circuit for a poly-phase direct current motor in a pulse width modulation mode and determining that a zero crossing will occur within a predetermined interval. The method also includes steps of enabling a bias current to a transconductance operational amplifier and changing an operating state of the drive circuit from the pulse width modulation mode to a linear mode. The method further includes steps of determining that the zero crossing has occurred, disabling the bias current to the transconductance operational amplifier and changing the operating state of the drive circuit from the linear mode to the pulse width modulation mode.

Abstract: An integrated circuit package with a path of high thermal conductivity is disclosed. A thermally conductive slug, formed of a material such as copper, is attached to an underside portion of a substrate, such as a printed circuit board or a ceramic substrate, through which an opening has been formed. An integrated circuit chip is mounted to one side of the slug exposed in the opening. An opposing surface of the slug lies below the plane of the underside of the substrate. The chip is wire bonded to the substrate, and is encapsulated in the conventional manner. Solder balls are attached to a portion of the underside of the substrate not covered by the slug in a ball-grid-array manner, for mounting to a circuit board. Upon mounting to the circuit board, a path of high thermal conductivity is provided between the chip and the circuit board, through the slug and the solder balls.

Abstract: A precision oscillator includes a capacitor, a charging current source, a discharging current source, a switch for alternatingly connecting the capacitor to the charging current source and the discharging current source, and a hysteretic comparator connected to the capacitor for producing an oscillating signal responsive to charging and discharging the capacitor. The oscillator may also preferably include a duty cycle controller connected to at least one of the charging current source and the discharging current source for setting the charging current and/or the discharging current to thereby set a duty cycle of the oscillating signal by setting a ratio of the charging and discharging currents. The charging current source may have a current setting input for permitting setting of a charging current to the capacitor, and the discharging current source may have a current setting input for permitting setting of a discharging current from the capacitor.