Patents Assigned to STMicroelectronics International N.V.
  • Publication number: 20210286417
    Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 16, 2021
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ankur BAL, Vikas CHELANI
  • Patent number: 11121687
    Abstract: Disclosed herein is a circuit including a differential amplifier having a pair of input transistors coupled in a differential arrangement between adjustable current sources and receiving input differential signals from a pair of input voltage regulators. The adjustable current sources are configured to source more current to the pair of input transistors than current that is sunk from the pair of input transistors. A first amplifier has inputs coupled to receive differential output voltages from the differential amplifier. A second amplifier has inputs coupled to receive amplified differential output voltages from the first amplifier. A low pass filter has inputs coupled to receive further amplified differential output voltages from the second amplifier and produce final differential output voltages.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Riju Biswas, Ratul Mitra
  • Patent number: 11119153
    Abstract: A method of testing a multiple power domain device includes sending a control signal from a test controller powered by a switchable power domain to a non-scan test data register powered by an always on power domain. The method further includes setting, using the control signal, a test data register value of the register to enable scan mode by bypassing an isolation cell between an output of the switchable domain and an input of the always on domain and, while the register value continuously enables scan mode: shifting a test pattern into a scan chain including a flip-flop coupled to the isolation cell, capturing a test result from the scan chain, and shifting the test pattern out of the scan chain to observe the test result. The isolation cell is configured to allow or disallow propagation of a signal from the output to the input.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 14, 2021
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Venkata Narayanan Srinivasan
  • Publication number: 20210281172
    Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.
    Type: Application
    Filed: May 6, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics International N.V.
    Inventor: Vikas RANA
  • Publication number: 20210281254
    Abstract: A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 9, 2021
    Applicant: STMicroelectronics International N.V.
    Inventors: Jeet Narayan TIWARI, Anand KUMAR, Prashutosh GUPTA
  • Patent number: 11107613
    Abstract: A resistance trimming circuit has a resolution of N=X+Y bits. Included is a first circuit with M resistors, where M=2X?1, with each of the M resistors having a resistance of R*(2Y)*i, i being an index having a value ranging from 1 to 2X?1. M switches are associated with the M resistors. Each of the M resistors is coupled between a first node and its one of the M switches, and each of the M switches couples its one of the M resistors to a second node. Included is a second circuit with P resistors, where P=2Y?1, with each of the P resistors having a resistance of R*i. P switches are associated with the P resistors. Each of the P resistors is coupled between the second node and its one of the P switches, and each of the P switches selectively couples its one of the P resistors to a third node.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 31, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Mohit Kaushik, Anil Kumar
  • Publication number: 20210265947
    Abstract: Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.
    Type: Application
    Filed: February 15, 2021
    Publication date: August 26, 2021
    Applicant: STMicroelectronics International N.V.
    Inventors: Gagan MIDHA, Anurup MITRA, Kallol CHATTERJEE
  • Patent number: 11096593
    Abstract: Motion activity data is collected from at least one sensor. An initial motion activity classifier function is applied to the motion activity data to produce an initial motion activity posteriorgram. Pre-processing and segmenting the motion activity data into windows produces segmented motion activity data from which sensor specific features are extracted. An updated motion activity classifier function is generated from the extracted sensor specific features. Subsequent motion activity data is also collected from the at least one sensor, and the updated motion activity classifier function is applied to the subsequent motion activity data to produce an updated motion activity posteriorgram.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 24, 2021
    Assignees: STMicroelectronics, Inc., STMicroelectronics International N.V.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Rajendar Bahl
  • Patent number: 11102617
    Abstract: This application discloses systems, devices, and methods for indoor navigation and tracking with a mesh network. In one aspect, a navigation device includes a receiver configured to receive a locational signal from a node network. The locational signal identifies a respective node of the node network, and the node network is distributed throughout a physical space. The navigation device includes a memory storing a program and a processor in communication with the receiver and configured to execute the program to calculate a position of the navigation device from the identity of the respective node, determine a routing instruction from the position of the navigation device to a destination based on the position of the navigation device and a known mapping of the node network in the physical space, and update the position of the navigation device and the routing instruction as the navigation device moves through the physical space.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 24, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Jitendra Jain, Alok Kumar Mittal
  • Patent number: 11094354
    Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
  • Patent number: 11094376
    Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Anuj Grover, Tanmoy Roy, Nitin Chawla
  • Patent number: 11092993
    Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Patent number: 11095297
    Abstract: A voltage controlled oscillator (VCO) circuit generates an output signal having a frequency which is dependent on a control voltage. A current is generated which is itself dependent on an amplitude of the VCO circuit. The generated current accordingly tracks, to an extent, the temperature behavior of the oscillator within the VCO circuit. The oscillator is driven by the sum of the generated current and a control current dependent on the control voltage. The control voltage may, for example, be generated by a phase lock loop (PLL).
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Sagnik Mukherjee
  • Publication number: 20210250036
    Abstract: A circuit includes an amplifier having first and second inputs and an output, and a feedback circuit configured to generate a feedback voltage in response to a voltage at the output of the amplifier. The feedback circuit is coupled to the first input of the amplifier to provide the feedback voltage to the first input of the amplifier. An output circuit is configured to generate a variable bias current in response to the voltage at the output of the amplifier. A switch circuit is configured to switch the second input of the amplifier from receiving a first reference voltage during a first mode of operation to receiving a second reference voltage during a second mode of operation.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 12, 2021
    Applicant: STMicroelectronics International N.V.
    Inventors: Anand KUMAR, Ramji GUPTA
  • Publication number: 20210248104
    Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.
    Type: Application
    Filed: January 7, 2021
    Publication date: August 12, 2021
    Applicants: STMicroelectronics International N.V., STMicroelectronics (Rousset) SAS
    Inventors: Manoj KUMAR, Kailash KUMAR, Nicolas DEMANGE
  • Patent number: 11085769
    Abstract: A gyroscope includes a substrate, a first structure, a second structure and a third structure elastically coupled to the substrate and movable along a first axis. The first and second structure are arranged at opposite sides of the third structure with respect to the first axis A driving system is configured to oscillate the first and second structure along the first axis in phase with one another and in phase opposition with the third structure. The first, second and third structure are provided with respective sets of sensing electrodes, configured to be displaced along a second axis perpendicular to the first axis in response to rotations of the substrate about a third axis perpendicular to the first axis and to the second axis.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: August 10, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS, INC., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Carlo Valzasina, Huantong Zhang, Matteo Fabio Brunetto, Gert Ingvar Andersson, Erik Daniel Svensson, Nils Einar Hedenstierna
  • Publication number: 20210239540
    Abstract: Circuitry generates base-to-emitter voltages (Vbe1, Vbe2) of two BJTs biased at different current densities, a base-to-emitter voltage (Vbe) of a BJT biased so Vbe is complementary to absolute temperature and has a curved non-linearity across temperature, and base-to-emitter voltages (Vbe1_c, Vbe2_c) of two BJTs biased by a temperature independent constant current and a current proportional to absolute temperature so Vbe2_c?Vbe1_c has the same but opposite curved non-linearity across temperature as Vbe. A sampling circuit samples these voltages and provides them to inputs of a loop filter. Filter outputs are quantized to produce a bitstream.
    Type: Application
    Filed: December 29, 2020
    Publication date: August 5, 2021
    Applicant: STMicroelectronics International N.V.
    Inventors: Atul DWIVEDI, Pijush Kanti PANJA
  • Patent number: 11081881
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit including a trigger actuated MOSFET device. Triggering of the MOSFET device is made in response to detection of either a positive ESD event or a negative ESD event.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 3, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Divya Agarwal, Radhakrishnan Sithanandam
  • Patent number: 11082006
    Abstract: A clock signal is generated with an oscillator. A crystal oscillator core within the oscillator circuit is switched on to produce first and second oscillation signals that are approximately opposite in phase. When a difference between a voltage of the first oscillation signal and a voltage of the second oscillation signal exceeds an upper threshold range, the crystal oscillator core is switched off. When the difference between the voltage of the first oscillation signal and the voltage of the second oscillation signal falls below the upper threshold range, the crystal oscillator core is switched back on. This operation is repeated so as to produce the clock signal.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 3, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Jain
  • Patent number: 11075624
    Abstract: A hybrid driver receives complementary high-speed input data signals and a pair of low-speed input data signals and selects one of the pairs of input data signals and drives output data signals on first and second output nodes based on the selected pair of input data signals. The hybrid driver includes first and second driver circuits coupled to the first and second output nodes, respectively. Each driver circuit includes first and second series-connected transistors coupled between a first supply voltage node and a reference voltage node, with an interconnection of the first and second series-connected transistors coupled to the corresponding first or second output node. Each first and second driver circuit includes a third transistor coupled in parallel with the corresponding first transistor. Each first and third transistor couples in parallel the corresponding output node to a second supply voltage node responsive to the corresponding low-speed input data signal.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: July 27, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Saiyid Mohammad Irshad Rizvi, Manish Garg