Abstract: A wireless charging transmitter device is includes a square wave signal generation circuit. The square wave signal generation circuit is formed by a first PMOS transistor switching circuit having a group of PMOS performance transistors and at least one PMOS functionality transistor, and a second NMOS transistor switching circuit having a group of NMOS performance transistors and at least one NMOS functionality transistor.

Abstract: A half-bridge driver circuit periodically repeats switching cycles by closing a first FET via a first drive signal, detecting an instant when a current flowing through the first FET reaches a threshold and then opening the first FET and closing a second FET via a second drive signal. An error amplifier generates a control voltage by comparing a feedback signal with a reference signal, and a variable current generator generates a first current as a function of the control voltage. The error amplifier includes a proportional-integral controller, and a slope compensation circuit that generates a second current as a ramp signal. The threshold is generated by subtracting the second current from the first current. In response to detecting the instant, the second current is sampled and a signal indicative of the threshold is generated by subtracting the sampled second current from the first current.

Abstract: At least one transmission of scrambled data with a pseudo-random sequence generated by a scrambling polynomial and an initialization value is performed between a transmitter and a receiver. Prior to the transmission, transmitter and the receiver engage in a secret negotiation phase to specifically determine the scrambling polynomial and the initialization value for the at least one transmission.

Abstract: An integrated circuit includes a semiconductor substrate and at least one memory cell provided with a vertical gate selection transistor buried in the substrate and a floating gate state transistor. The floating gate state transistor covers a first active region and a second active region of the substrate delimited by lateral isolation regions. The memory cell includes a lateral isolation region thickness (in breadth) dimension between a sidewall of the vertical gate of the buried transistor and the second active region.

Abstract: A microelectromechanical device includes: a supporting body, containing semiconductor material; a movable mass, constrained to the supporting body with a relative degree of freedom with respect to a first motion direction perpendicular to the supporting body; and at least one stopping structure, configured to limit out-of-plane movements of the movable mass along the first motion direction. The stopping structure includes: first elements, extending parallel to the first motion direction and anchoring the stopping structure to the supporting body; and a second element, extending transversally to the first elements, surmounting and connecting the first elements.

Abstract: Articles carried by a carrier are processed in a sequence of processing steps that includes a plating step where a base layer of plating material is plated on a surface of the carrier. The plating material plated on the surface of the carrier is selectively stripped to partially remove the plating material to reduce e thickness of the base layer of plating material plated present on the surface of the carrier. A residual protective layer of plating material having the reduced thickness is left on the surface of the carrier.

Abstract: MEMS device having a substrate of semiconductor material; a first structural layer of semiconductor material, on the substrate; a second structural layer of semiconductor material, on the first structural layer; an active portion, accommodating active structures formed in the first structural layer and/or in the second structural layer; a connection portion, accommodating a plurality of connection structures and arranged laterally to the active portion; and a plurality of conductive regions, arranged on the substrate and extending between the active portion and the connection portion. Each connection structure is formed by a first connection portion, in electrical contact with a respective conductive region and formed in the first structural layer, and by a second connection portion, on the first connection portion and in electrical continuity therewith, the second connection portion formed in the second structural layer. The first connection portion has a greater thickness than the second connection portion.

Abstract: A circuit detects zero crosses in an input-signal and includes a low-pass-filter (LPF) receiving the input-signal and introducing a phase-shift dependent on the frequency thereof. Filter circuitry receives the output of the LPF, applies a fixed phase-shift thereto, and adjusts phase and DC-offset thereof based on control signals to produce a filtered output-signal. Control circuitry has a zero-crossing detector receiving the input-signal and the filtered output-signal, detecting zero-crossings of the input-signal and the filtered output-signal, asserting a digital zero cross signal at each zero crossing, and determining a phase-shift and DC-offset between the input-signal and filtered output-signal.

Abstract: A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

Abstract: The integrated circuit includes a power amplifier, an antenna, and a matching and filtering network including a direct current power supply stage on an output node of the power amplifier, a first section, and a second section. The direct current power supply stage and the two sections include inductor-capacitor “LC” arrangements configured to have an impedance that is matched to the output of the power amplifier in the fundamental frequency band. The LC arrangements of the direct current power supply stage and of the first section are furthermore configured to have resonant frequencies that are respectively adapted to attenuate harmonic frequency bands of the fundamental frequency band.

Abstract: A system-on-a-chip includes a first digital domain and a second digital domain. An interface circuit includes a level-shifting circuit for converting a signal between the first digital domain and the second digital domain. The first digital domain includes a control circuit configured to generate a control signal for transmission to the second digital domain. The control signal includes a pulse having a nominal duration adapted to the level-shifting circuit. At the input of the level-shifting circuit, the interface circuit includes, in the first domain, a conditional pulse-stretching circuit that lengthens a duration of the pulse of the control signal to at least the nominal duration when a duration of the pulse of the control signal is shorter than the nominal duration and non-zero.

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

Abstract: The present description relates to a method of manufacturing an electronic device comprising a phase-change memory cell, the method comprising: the forming of a first layer made of a resistive material; the forming of a stack of layers on the first layer, the stack comprising at least one second layer made of a phase-change material; the etching of the stack, said etching stopping when the first layer is reached around the location of the memory cell; the forming of a spacer on the side walls of the stack; then an etching of the first layer, so that the stack rests on a central portion of the first layer and that the spacer rests on a peripheral portion of the first layer.

Abstract: The present disclosure is directed to cough detection for electronic devices, such as wireless headphones. The cough detection utilizes inertial sensors to perform both head movement detection and vocal activity detection. The dual identification of head movement and vocal activity allows improved detection accuracy, and minimal false detections caused by environmental noise.

Abstract: A method, comprising: coupling a set of sensing circuits to a set of electronic devices; sensing, via the sensing circuits, a set of sensing signals indicative of an operating state of the set of electronic devices; applying logic signal processing to the set of sensing signals via coupling a set of signal processing channels to the set of sensing circuits and providing a set of logically combined sensing signals as a result, wherein the logically combined sensing signals are indicative of whether the operating state of the electronic devices in the set of electronic devices is an expected operating state or an unexpected operating state; coupling the set of logically combined sensing signals to a set of input channels of a fault collection and control unit, FCCU; storing at least one data structure comprising data related to the way in which the set of input channels of the FCCU are coupled to the set of sensing circuits via the set of signal processing channels.

Abstract: A process for forming a high electron mobility transistor (HEMT) includes forming a semiconductor heterostructure including a channel layer of the HEMT, forming a gate layer of GaN on the channel layer, and patterning the gate layer to form a first gate finger, a second gate finger, and a gate arc connecting the first gate finger and the second gate finger. The process includes forming an isolation mask covering an active region of the semiconductor heterostructure and the gate arc and performing an ion bombardment process on an inactive region of the semiconductor heterostructure exposed by the isolation mask.

Abstract: A MOSFET transistor with a semiconductor body including a drain region of a first conductivity type, delimited by a front surface, and at least one cell including: a pair of gate structures laterally offset parallel to a first axis and each including a respective gate dielectric region, arranged on the front surface, and a respective gate conductive region, arranged on the corresponding gate dielectric region; a body structure of a second conductivity type, which includes a body region, which extends inside the drain region starting from the front surface and contacts portions of the gate dielectric regions, and a strengthening region, which extends below the body region; and a pair of source regions of the first conductivity type, which extend inside the body region starting from the front surface.

Abstract: An electronic vehicle includes A DC link capacitor and a traction inverter coupled to the DC link capacitor. The traction inverter includes a first half bridge circuit, a second half bridge circuit, and a third half bridge circuit each coupled between terminals of the DC link capacitor. The traction inverter includes a driver circuit coupled to the traction inverter configured to drive the first, second, and third half bridge circuits to generate an AC voltage in a standard operating mode. The driver circuit is configured to discharge the DC link capacitor responsive to a discharge command by toggling the first half bridge between an open condition and a closed condition while holding the second half bridge circuit and the third half bridge circuit in the open condition.