Abstract: Described herein is an operational transconductance amplifier (OTA) with a constant current source that provides a constant current to a node. The OTA includes two input pairs of transistors: the first sources variable currents based on feedback and input voltages, while the second sinks variable currents also based on feedback and input voltages. A folded cascode arrangement includes two branches, with one branch including a Monticelli cell. A class-AB output stage is present, with its inputs connected across the Monticelli cell. Additionally, a bias stage mirrors and scales the constant current to generate control voltages. Within the folded cascode branches, compensation transistors are controlled by these control voltages, ensuring that various sourced and sunk variable currents are of equal magnitude, making the OTA input voltage independent.

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

Abstract: Lateral isolation regions are formed in a semiconductor substrate to delimiting active regions of the semiconductor substrate. A trench is then etched extending vertically in depth in the substrate through the lateral isolation regions and the active regions. The formation of the lateral isolation regions is configured to provide, at the location of where the etching of the trench is to be performed, enlarged portions of the lateral isolation regions delimiting thinned portions of the active regions. As a result, the bottom of the trench has a form having variations in depth with low portions facing the location of the trench that passes through the lateral isolation regions, and high portions facing the location of the trench that passes through the active regions.

Abstract: Disclosed is a receiver that includes a pre-amplifier circuit and an amplifier circuit. The pre-amplifier circuit includes first and second input terminals that receive signals from a transmitter; first and second output terminals that output signals to the amplifier circuit; a first resistor having a first terminal coupled to the first input terminal, and a second terminal coupled to a first node; a second resistor having a first terminal coupled to the second input terminal, and a second terminal coupled to the first node; a third resistor having a first terminal coupled to the first output terminal, and a second terminal coupled to a second node; a fourth resistor having a first terminal coupled to the second output terminal, and a second terminal coupled to the second node; and a switch having a first terminal coupled to the first node, and a second terminal coupled to the second node.

Abstract: A microelectromechanical membrane sensor includes: a supporting body, containing semiconductor material and having a recess in a face; a platform, housed in the recess at a distance from the supporting body; a flexure, connecting the platform to the supporting body and configured to keep the platform suspended in the recess. A gap extends between the supporting body, the platform and the flexure. A membrane is housed in the platform and delimits a buried cavity incorporated in the platform. A sealing strip extends on the supporting body, on the platform and on the flexure along the gap.

Abstract: According to one aspect, provision is made of a timing method implemented by a computer system comprising: a central processing unit, an external clock circuit comprising a counter, the counter being configured to increment or decrement its value with each clock stroke of the external clock circuit over a range of values corresponding to one millisecond, the timing method comprising: defining a maximum number of transitions of a bit to be monitored of the counter value corresponding to a desired waiting delay, monitoring transitions of the bit to be monitored of the counter value so as to achieve the timing until the number of performed transitions of the bit to be monitored reaches the defined maximum number of transitions.

Abstract: A microelectromechanical motion sensor device is described, provided with: a base substrate having a front surface with extension in a horizontal plane; and a sensing structure arranged above the base substrate, for sensing components of a motion quantity along respective sensing axes. The sensing structure is provided with: a housing element integrally coupled above the front surface of the base substrate and internally defining a cavity; a single mobile mass arranged inside the cavity; an elastic supporting arrangement arranged above the mobile mass, with main extension in a plane overlying the mobile mass to elastically support the mobile mass inside the cavity, so that it is suspended above the front surface of the base substrate and performs, due to inertial effect, a respective sensing movement in response to each of the components of the motion quantity; and a sensing electrode arrangement, capacitively coupled to the mobile mass for sensing the components of the motion quantity.

Abstract: A process for manufacturing a combined microelectromechanical device envisages: forming, in a sensor wafer, at least a first and a second microelectromechanical structures, at a main surface; forming, in a cap wafer, at least a first and a second cavities, at a respective main surface; forming a getter region inside the first cavity; bonding the main surfaces of the sensor and cap wafers by means of a bonding region, to define a first and a second hermetic environments for the microelectromechanical structures at different pressure values. A raised frame is formed, before the bonding step, in such a way as to be located around the first cavity; the bonding region determines the bonding of the sensor and cap wafers at the raised frame and the definition of the first hermetic environment associated with the first cavity, in a time interval prior to hermetic closure of the second cavity.

Abstract: A method of authentication of a first device to a second device uses a signature of an analog signal of the first device. The signature corresponds to a time variation of at least one physical quantity associated with the analog signal during the implementation of at least one specific operation. The at least one specific operation may be an implementation of an electronic function or a program.

Abstract: A method for manufacturing a SiC-based electronic device, comprising the steps of: implanting, on a front side of a solid body made of SiC having a conductivity of an N type, dopant species of a P type thus forming an implanted region, which extends in the solid body starting from the front side and has a top surface coplanar with the front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region to temperatures comprised between 1500° C. and 2600° C. so as to form a carbon-rich electrical-contact region at the implanted region. The carbon-rich electrical-contact region forms an ohmic contact.

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Abstract: A deep trench isolation structure is formed in a semiconductor material body by opening first and second trenches. The sidewalls and bottoms of the first and second trenches are then lined with an insulating material. A halogen-based polymer material is then deposited to cover at least an upper portion of the insulation material in the first trench without covering a portion insulation material at the bottom of the first trench and further cover the insulation material at the sidewalls and bottom of the second trench. An etch process is then used to remove the portion of the insulation material at the bottom of the first trench and the polymer material is removed from both the first trench and second trench. The trenches are then filled with polysilicon to form a substrate plug in the first trench and a field plate electrode in the second trench.

Abstract: Process for manufacturing electronic components with wettable flanks from a substrate covered by connection terminals and in which chips are formed, the process comprising the following steps: a) solder connection pads to the connection terminals, b) coat the connection pads with a layer of insulating resin, c) thin the insulating resin layer until it reaches the core of the connection pads, d) form cavities by removing part of the connection pads and part of the insulating resin layer, so as to make part of the flanks of the components accessible, e) deposit a layer of conductive material on the flanks of the components and on the connection pads, f) separate the chips.

Abstract: A power module including a rigid-flexible PCB that exits from a resin molding case, and includes a first PCB region having a stacked structure of piled up layers; a second PCB region having said stacked structure, further locally delimited at a first side by a top stiffening element and at a second opposite side by a bottom stiffening element; and a third PCB region having said stacked structure without the top and bottom stiffening elements. The top and bottom stiffening elements extend at a lateral surface of the molding case, where the PCB exits from the molding case, and are configured to locally increase the rigidity of the PCB with respect to regions of the PCB 20 where said top and bottom stiffening elements are absent. A power module and method of manufacturing the power module is also provided.

Abstract: The present disclosure is directed to a MEMS device having a first and a second actuator element, of piezoelectric type and a first and a second arm. The first and a second actuator element are configured to generate respective alternate, approximately linear, movements of an own end portion along a first and, respectively, a second direction, the second direction transverse to the first direction. The first arm has a first end rigid with the end portion of the first actuator element. The second arm extends transversally to the first arm and has a first end coupled rigid with the end portion of the second actuator element and a second end coupled rigid with the first arm. The first and the second actuator elements are configured to be driven in an offset manner, so that the second end of the first arm performs a movement along a closed line.

Abstract: Disclosed is an apparatus including a plurality of channels that drive one or more electrical loads and a control module that generates control signals to operate at least one channel in the plurality of channels, an electronic fuse that monitors one or more operating parameter in a respective channel and detects anomalous conditions in that channel based on the parameter(s) monitored, and a parallel-mode block that defines one or more sets of channels including two or more channels configured to drive a same load. The control module receives from the parallel-mode block parallel-mode management control signals and operates the channels in the set of channels based on parallel-mode management control signals received by the parallel-mode block. The electronic fuse makes the channels in the set of channels non-conductive in response to an anomalous condition detected even in just one channel in the set.

Abstract: A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.

Abstract: The present description concerns an operating method of a non-volatile memory, comprising the validation of a transaction, requesting a modification of a value of configuration of a sector of the memory, after comparison of the attributes of the transaction with access attributes of said sector of said memory.

Abstract: An electronic component includes a gate structure over a semiconductor layer. The gate structure is insulated from the semiconductor layer and includes a layer made of a magnetic material. The electronic component may form a FET transistor, a MOSFET transistor, a SET transistor, a gated diode, a gated MOS structure, or a gated quantum dot.

Abstract: A process for a slave device on a serial data bus to make an in-band interrupt request to a master device includes checking whether a backoff time stored by a backoff timer has expired. When the backoff time has not expired, the slave device refrains from initiating the in-band interrupt request to the master device in response to a start condition on the serial bus. However, when the backoff time has expired, the slave device is permitted to initiate the in-band interrupt request to the master device in response to the start condition on the serial bus.