Patents Assigned to STMicroelectronics International N.V.
  • Patent number: 10530366
    Abstract: A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: January 7, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Atul Dwivedi, Paras Garg, Kallol Chatterjee
  • Patent number: 10531132
    Abstract: A channel stream is received and demultiplexed into a video packetized elementary stream (PES), audio packetized elementary stream (PES), and program clock reference (PCR). Indexing circuitry stores the video PES and the audio PES in a buffer, locates a presentation time stamp (PTS) in the video PES and stores that PTS in the buffer, locates a start of each group of pictures (GOP) in the video PES and stores those locations in the buffer, and locates a PTS in the audio PES and stores that PTS in the buffer. Control circuitry empties the buffer of an oldest GOP in the video PES if the PCR is greater than the PTS of a second oldest GOP stored in the buffer, and empties the buffer of each PES packet of the audio PES that has a PTS that is less than the PTS of the oldest GOP stored.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 7, 2020
    Assignees: STMicroelectronics International N.V., STMicroelectronics, Inc.
    Inventors: Udit Kumar, Bharat Jauhari, Chandandeep Singh Pabla
  • Patent number: 10527672
    Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: January 7, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Srinivas Dhulipalla
  • Publication number: 20200006339
    Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.
    Type: Application
    Filed: June 24, 2019
    Publication date: January 2, 2020
    Applicant: STMicroelectronics International N.V.
    Inventor: Vishal Kumar SHARMA
  • Patent number: 10520552
    Abstract: An electronic device includes a processor coupled to a battery and to determine whether the battery is being charged or discharged. If the battery being is being discharged, the processor operates to calculate an amount by which the battery has discharged since a preceding calculation of remaining capacity of the battery, compensate the amount by which the battery has discharged for a condition of the battery, and calculate a remaining capacity of the battery as a function of the amount by which the battery has discharged. If the battery is being charged, the processor operates to calculate an amount by which the battery has charged since a preceding calculation of remaining capacity of the battery, compensate the amount by which the battery has charged for a condition of the battery, and calculate the remaining capacity of the battery as a function of the amount by which the battery has charged.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 31, 2019
    Assignees: STMicroelectronics, Inc., STMicroelectronics International N.V.
    Inventors: K. R. Hariharasudhan, Frank J. Sigmund
  • Publication number: 20190393779
    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
    Type: Application
    Filed: September 6, 2019
    Publication date: December 26, 2019
    Applicant: STMicroelectronics International N.V.
    Inventor: Vikas RANA
  • Publication number: 20190384347
    Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 19, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Rupesh SINGH
  • Publication number: 20190379358
    Abstract: A cascaded integrator-comb (CIC) decimation filter includes N integrator stages, N?1 differentiator stages, and a decimator coupled to receive an integrated signal that is output from the N integrator stage and generate a decimated signal that is input to the N?1 differentiator stages. The decimator periodically asserts an integration reset signal. A last integrator stage of the N integrator stages is reset in response to assertion of the integration reset signal.
    Type: Application
    Filed: May 20, 2019
    Publication date: December 12, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Vikram SINGH, Harvinder SINGH
  • Publication number: 20190379277
    Abstract: Disclosed herein is a circuit including a transistor, with a resonant tank coupled between a DC supply node and a first conduction terminal of the transistor. A gate driver generates a gate drive signal for biasing a control terminal of the transistor to cause it to conduct current through the resonant tank. Control circuitry monitors a voltage across the transistor to determine that the transistor is an overvoltage condition if that voltage exceeds a threshold, and monitors a current through the transistor to determine that the transistor is an overcurrent condition if that current exceeds a threshold. If overvoltage is determined, the control circuitry causes the gate driver to pull up the gate drive signal. If overcurrent is determined, the control circuitry causes the gate driver to pull down the gate drive signal. If either overvoltage or overcurrent is present, a pulse width of the gate drive signal is reduced.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 12, 2019
    Applicant: STMicroelectronics International N.V.
    Inventor: Akshat JAIN
  • Patent number: 10505552
    Abstract: An electronic device disclosed herein includes a locked loop circuit configured to receive a reference signal intended to have an intended frequency, wherein the locked look circuit is intended to generate an intended output signal having an intended frequency equal to the intended frequency multiplied by an intended multiplier. A frequency counter counts a number of pulses of the reference signal during a time window so as to determine an actual frequency of the reference signal. A control circuit determines an actual multiplier for the locked loop circuit that, when multiplied by the actual frequency of the reference signal, causes the locked loop circuit to generate an actual output signal having an actual frequency equal to the intended frequency.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Nitin Gupta, Nitin Jain
  • Patent number: 10502784
    Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Satinder Singh Malhi
  • Patent number: 10505562
    Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 10, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 10504031
    Abstract: An electronic device described herein includes a sensing unit having at least one sensor to acquire sensing data. An associated computing device extracts sensor specific features from the sensing data, and generates a motion activity vector, a voice activity vector, and a spatial environment vector as a function of the sensor specific features. The motion activity vector, voice activity vector, and spatial environment vector are processed to determine a base level context of the electronic device relative to its surroundings, with the base level context having aspects each based on the motion activity vector, voice activity vector, and spatial environment vector. Meta level context of the electronic device relative to its surroundings is determined as a function of the base level context, with the meta level context being at least one inference made from at least two aspects of the plurality of aspects of the base level context.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 10, 2019
    Assignees: STMicroelectronics International N.V., STMicroelectronics, Inc.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Kashif R. J. Meer, Indra Narayan Kar, Rajendar Bahl
  • Patent number: 10495690
    Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debugging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Manish Sharma
  • Patent number: 10498312
    Abstract: A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Mohit Singh, Ankur Bal
  • Patent number: 10484165
    Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Rupesh Singh, Ankur Bal
  • Patent number: 10482819
    Abstract: A device includes a matrix of active pixels, with each active pixel having an OLED diode having a cathode to receive a cathode voltage, and a control circuit coupled to an anode of the OLED diode. The device also includes at least one dummy pixel having a dummy OLED diode having a cathode to receive the cathode voltage, and an anode, and a dummy control circuit coupled to the anode of the OLED diode and having a power supply terminal. The dummy OLED diode and the dummy control circuit are substantially similar to the OLED diode and the control circuit. First regulation circuitry is configured to deliver a reference current to the power supply terminal to thereby generate a voltage, and second regulation circuitry is configured to regulate the cathode voltage so as to maintain the voltage at the power supply terminal at a given level.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 19, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Jerome Nebon, Jean-Marie Permezel
  • Publication number: 20190342960
    Abstract: A circuit includes a voltage converter converting a source voltage to a supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between the first node and a second node. Feedback circuitry compares the voltage at the second node to first and second overvoltages, and selectively couples the second node to the feedback node based thereupon. Impedance circuitry is coupled between the first node and a third node. A light emitting diode (LED) chain is coupled to the third node, and is selectively turned on and off as a function of the selective coupling of the second node to the feedback node by the feedback circuitry.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Akshat JAIN, Ranajay MALLIK
  • Patent number: 10468095
    Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: November 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
  • Publication number: 20190334509
    Abstract: A ring oscillator circuit is formed by series connected inverter circuits with a feedback loop. The inverter circuits are source biased with an oscillator voltage. A resistor-less bias current generator circuit generates a bias current for application to a replica inverter circuit to generate a bias voltage. A scaling circuit operates to scale the bias voltage by a selectable scaling factor to generate the oscillator voltage in a manner which balances a mobility effect of the inverter circuits within the ring oscillator circuit against a threshold voltage effect of the inverter circuits within the ring oscillator circuit. The clock signal output from the ring oscillator circuit has a frequency which is independent of process, voltage and temperature (PVT) spread.
    Type: Application
    Filed: April 25, 2018
    Publication date: October 31, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin GUPTA, Nitin JAIN