Patents Assigned to STMicroelectronics International N.V.
  • Publication number: 20200118617
    Abstract: A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 16, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Shishir KUMAR, Bhupender SINGH
  • Patent number: 10620267
    Abstract: A method of operating an electronic device during test mode operation of a duplicated voltage monitor includes sensing a functional supply voltage with a voltage monitor, deasserting an output of the voltage monitor if the functional supply voltage is exceeds a threshold, and asserting output of the voltage monitor if the functional supply voltage falls below the threshold. A test supply voltage is sensed with the duplicate voltage monitor, output of the duplicate voltage monitor is deasserted if the test supply voltage exceeds a threshold, and output of the duplicate voltage monitor is asserted if the test supply voltage falls below the threshold. Output of the duplicate voltage monitor is monitored to thereby determine the threshold based upon assertion of the output of the duplicate voltage monitor, and performing a logical operation between outputs of the voltage monitor and the duplicate voltage monitor to generate a power on reset signal.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Srinivas Dhulipalla
  • Patent number: 10623218
    Abstract: A demodulator circuit receives an envelope signal for comparison against a switched reference signal that is generated as a function of the envelope signal and as a function of an output signal of the demodulator circuit. The switched reference signal is filtered by an RC filter prior to comparison. The output signal is dependent on a difference between the filtered switched reference signal and the envelope signal.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: April 14, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Vinko Kunc, Albin Pevec, Kosta Kovacic
  • Publication number: 20200110663
    Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Om RANJAN, Riccardo GEMELLI, Denis DUTEY
  • Patent number: 10615809
    Abstract: Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 7, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Ankit Gupta, Anand Kumar
  • Patent number: 10608637
    Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 31, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Prashant Singh, Pratap Narayan Singh
  • Patent number: 10608705
    Abstract: An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 31, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Kosta Kovacic, Albin Pevec, Maksimiljan Stiglic
  • Publication number: 20200099378
    Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 26, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Shishir KUMAR, Tanuj KUMAR, Deepak Kumar BIHANI
  • Patent number: 10588517
    Abstract: Described herein is a method of operating an electronic device that includes collecting initial motion activity data from at least one sensor of the electronic device, and generating a initial probabilistic context of the electronic device relative to its surroundings from the initial collected motion activity data using a motion activity classifier function. The collected motion activity data is stored in a training data set, and the motion activity classifier function is updated using the training data set. The method also includes collecting subsequent motion activity data from the at least one sensor of the electronic device, and generating a subsequent probabilistic context of the electronic device relative to its surroundings from the subsequently collected motion activity data using the updated motion activity classifier function.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 17, 2020
    Assignees: STMicroelectronics, Inc., STMicroelectronics International N.V.
    Inventors: Mahesh Chowdhary, Arun Kumar, Ghanapriya Singh, Rajendar Bahl
  • Patent number: 10585143
    Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 10, 2020
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pascal Urard, Florian Cacho, Vincent Huard, Alok Kumar Tripathi
  • Publication number: 20200073430
    Abstract: A sub-bandgap reference voltage generator includes a reference current generator generating a reference current (proportional to absolute temperature), a voltage generator generating an input voltage (proportional to absolute temperature) from the reference current, and a differential amplifier. The differential amplifier is biased by the reference current and has an input receiving the input voltage and a resistor generating a voltage proportional to absolute temperature summed with the input voltage to produce a temperature insensitive output reference voltage. The reference current generator may generate the reference current as a function of a difference between bias voltages of first and second transistors.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 5, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Pijush Kanti PANJA, Gautam Dey KANUNGO
  • Publication number: 20200076437
    Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.
    Type: Application
    Filed: November 5, 2019
    Publication date: March 5, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Anand KUMAR, Nitin GUPTA, Nitin JAIN
  • Publication number: 20200075090
    Abstract: A wordline coupled to a memory cell is selected in connection with performing a read/write operation at the memory cell. A wordline signal is asserted on the selected wordline. The assertion of the wordline signal has a leading edge and a trailing edge and, between the leading edge and trailing edge, a series of wordline underdrive pulses. Each wordline underdrive pulse causes a wordline voltage to fall from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level. The first and second voltage levels are both greater than a ground voltage of the memory cell.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 5, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Ashish KUMAR, Mohammad Aftab ALAM
  • Publication number: 20200064405
    Abstract: A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan SRINIVASAN, Manish SHARMA
  • Patent number: 10572440
    Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 25, 2020
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tejinder Kumar, Rathod Ronak Kishorbhai, Apurva Sen, Rakesh Malik
  • Patent number: 10566980
    Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Jeet Narayan Tiwari
  • Patent number: 10543504
    Abstract: A microfluidic die is disclosed that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 28, 2020
    Assignees: STMicroelectronics, Inc., STMICROELECTRONICS S.R.L., STMicroelectronics International N.V.
    Inventors: Simon Dodd, Joe Scheffelin, Dave Hunt, Matt Giere, Dana Gruenbacher, Faiz Sherman
  • Patent number: 10535416
    Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics International N.V.
    Inventor: Nishu Kohli
  • Publication number: 20200014387
    Abstract: A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.
    Type: Application
    Filed: July 5, 2019
    Publication date: January 9, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Atul DWIVEDI, Paras GARG, Kallol CHATTERJEE
  • Publication number: 20200014372
    Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.
    Type: Application
    Filed: July 5, 2018
    Publication date: January 9, 2020
    Applicant: STMicroelectronics International N.V.
    Inventors: Rajesh Narwal, Pravesh Kumar Saini