Patents Assigned to STMicroelectronics International N.V.
  • Publication number: 20240178178
    Abstract: An integrated circuit semiconductor dice has first and second opposed surfaces. First and second electrically conductive patterns extending at the first and second opposed surfaces provide electrical coupling to the semiconductor die. An electrical component, such as a capacitor, having a length transverse to the first and second opposed surfaces of the semiconductor die, extends bridge-like between the first and second opposed surfaces. Opposed electrical contact end terminals of the electrical component are coupled to the first and second electrically conductive patterns. The electrical component is thus electrically coupled to the semiconductor die via the first and second electrically conductive patterns at the first and second opposed surfaces.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 30, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Francesca DE VITI, Damian HALICKI, Giovanni GRAZIOSI, Michele DERAI
  • Publication number: 20240178092
    Abstract: Electronic device, comprising: a solid body including a Silicon Carbide substrate, and further including an electrical terminal of the electronic device on the substrate; a passivation layer on the electrical terminal, of a first material; and a first adhesion improving layer coupled to the passivation layer and to the solid body, of a second material having predefined characteristics of adhesion to the first material, and configured to bond together the passivation layer and the solid body.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 30, 2024
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Gabriele BELLOCCHI, Simone RASCUNA', Valeria PUGLISI
  • Publication number: 20240170446
    Abstract: The present description concerns a method of assembly of a first assembly layer comprising a first copper region at a first surface and of a second assembly layer comprising a second region made of oxide or of an oxidized metal at a second surface, wherein the first and second surfaces are assembled by means of a hybrid bonding such that the entire first copper region is placed into contact with the oxide or the oxidized metal of the second region.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 23, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Sandrine LHOSTIS, Bassel AYOUB, Laurent FREY
  • Publication number: 20240170960
    Abstract: An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 23, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Francois TAILLIET
  • Publication number: 20240171217
    Abstract: Provided is an electronic system including an electronic device and a reader. The electronic device includes a non-volatile memory; a first NFC module; and a first component adapted to receiving at least one signal sent by a sensor and adapted to converting said signal into digital data. When the electronic device receives said signal said component converts said signal into the data, and then stores said data into said non-volatile memory. The first module is adapted to supplying said reader with said data. The reader includes a second NFC module; and a second component adapted to implementing a digital filtering function. The second module is adapted to receiving said data and said second component is adapted to applying said function to said data.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 23, 2024
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Jose MANGIONE
  • Publication number: 20240170032
    Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location in response to assertion of control signal having a dynamically variable delay dependent on the current data word. The operations are advantageously performed within a single clock cycle.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 23, 2024
    Applicant: STMicroelectronics International N.V.
    Inventor: Praveen Kumar VERMA
  • Patent number: 11991028
    Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 21, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Iztok Bratuz, Vinko Kunc, Maksimiljan Stiglic
  • Patent number: 11989148
    Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: May 21, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Patent number: 11983025
    Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: May 14, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal
  • Patent number: 11984151
    Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: May 14, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj Ayodhyawasi
  • Patent number: 11977971
    Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: May 7, 2024
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.r.l
    Inventors: Surinder Pal Singh, Thomas Boesch, Giuseppe Desoli
  • Patent number: 11979167
    Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: May 7, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Sharad Gupta, Ankur Bal
  • Publication number: 20240143239
    Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 2, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Bhupender SINGH, Hitesh CHAWLA, Tanuj KUMAR, Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Manuj AYODHYAWASI, Nitin CHAWLA
  • Publication number: 20240146092
    Abstract: A circuit for use, e.g., as current sense amplifier in a DC-DC converter in a hybrid vehicle includes a first input node and a second input node, configured to have an input voltage signal applied therebetween, a floating-ground input stage configured to operate between a first supply voltage and a second non-zero supply voltage and to convert into a current signal the input voltage signal applied between the first input node and the second input node. The circuit includes an output stage configured to receive the current signal from the floating-ground input stage and to convert the current signal back to an output voltage signal referred to ground. The output voltage referred to ground is a replica of the input voltage signal applied between the first input node and the second input node.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 2, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Simone BIANCHI, Vanni POLETTO
  • Publication number: 20240146324
    Abstract: Offset calibration for an analog front-end system is provided. The analog front-end system includes a variable-gain amplifier, and the calibration mitigates an offset error of the variable-gain amplifier. Calibration is based on a difference-based estimation technique combined with digital iteration. Difference-based estimation includes measuring different digital output signals from an analog-to-digital converter for different respective gains of the variable-gain amplifier. The digital iteration is utilized to estimate offsets values which converge a digital output difference to a target of zero volts.
    Type: Application
    Filed: October 6, 2023
    Publication date: May 2, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Anubhuti CHOPRA
  • Publication number: 20240128971
    Abstract: An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 18, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Sameer VASHISHTHA, Saiyid Mohammad Irshad RIZVI, Paras GARG
  • Publication number: 20240112748
    Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.
    Type: Application
    Filed: July 31, 2023
    Publication date: April 4, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Tanuj KUMAR, Hitesh CHAWLA, Bhupender SINGH, Harsh RAWAT, Kedar Janardan DHORI, Manuj AYODHYAWASI, Nitin CHAWLA, Promod KUMAR
  • Publication number: 20240112728
    Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.
    Type: Application
    Filed: September 11, 2023
    Publication date: April 4, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Harsh RAWAT, Kedar Janardan DHORI, Dipti ARYA, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
  • Publication number: 20240113741
    Abstract: An integrated circuit includes a current mode transmitter. The current mode transmitter includes a first resistor and a second resistor. The resistance of the first resistor is adjusted by measuring the resistance, generating a resistance trimming code based on the measured resistance, and writing the first resistance trimming code to a first register. The resistance of the second resistor is adjusted by generating a second resistance trimming code based on the first resistance trimming code and writing the second resistance trimming code to a second register.
    Type: Application
    Filed: September 20, 2023
    Publication date: April 4, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Sameer VASHISHTHA, Kirtiman Singh RATHORE, Paras GARG
  • Patent number: 11933861
    Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 19, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Sharad Gupta