Abstract: The present description concerns an electronic circuit manufacturing method comprising, in the order, forming an opening in a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to the first surface, the opening positioned between the first surface and the second surface and forming an electrically-conductive pad, the electrically-conductive pad including a first portion positioned over the first surface and a second portion covering the flanks of the opening and delimiting a gap in the opening, and depositing a first layer covering the electrically-conductive pad and filling the gap, the first layer containing a first resin, the first resin being non-photosensitive, and crosslinking the first resin in the first layer, and chemically etching by plasma the first layer to delimit a first block of the first resin in the gap, and depositing a first protection layer on the first block.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: The present description concerns a bus error management method, wherein one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge, are stored, and wherein in the presence of a bus error sent by the functional unit: one or a plurality of second characteristics linked to said error are stored; the bridge generates a first interrupt that it transmits with said first and second characteristics to a management unit; and the management unit generates at least one second interrupt intended for a processing unit as a function of the first and/or second characteristics.

Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

Abstract: A read-modify-write operation is performed, within a single cycle of a clock signal, by: decoding an address to select a word line of a memory; applying a word line signal at a first voltage level to the selected word line; reading a current data word from a data word location in the memory; reducing the word line signal from the first voltage level to the second voltage level; performing a mathematical modify operation internally within the memory on the current data word to generate a modified data word; increasing the word line signal from the second voltage level to the first voltage level; and writing the modified data word back to the location in the memory.

Abstract: According to an embodiment, a method for determining an orientation of an object in a field-of-view of a time-of-flight sensor is proposed. The method includes receiving a sensor readout from the time-of-flight sensor; feeding the sensor readout as an input to a neural network, the neural network trained on a set of data with a binary output that classifies the input as being valid or invalid based on the orientation of the object with respect to the time-of-flight sensor; rotating the sensor readout for a set number of rotations and feeding each rotation as an input to the neural network to determine a valid orientation of the object; and rotating an image on a display interface based on the rotation corresponding to the valid orientation of the object as determined by the neural network.

Abstract: According to one aspect, a computer system is provided comprising: a data memory configured to store a byte array, a digital signal processor configured to execute a computer program stored in a program memory comprising instructions allowing accessing a bit in said byte array, said digital signal processor being configured to access each byte of said byte array, a dedicated circuit configured to read and/or write access a bit of a byte of said byte array using: a bit position pointer pointing towards the bit to be accessed in the byte array in combination, and said byte comprising the bit to be accessed.

Abstract: Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

Abstract: A manufacturing process for microelectromechanical devices includes: on a first wafer forming a structural layer and a stop layer; defining a stop pad from the stop layer; forming a first microelectromechanical structure and a second microelectromechanical structure in the structural layer; forming a contact element protruding from a second wafer; sealing, at a first pressure, the first microelectromechanical structure in a first chamber and the second microelectromechanical structure and the stop pad in a second chamber; fluidically coupling the second chamber to an external environment; and sealing the second chamber at a second pressure. Sealing at the first pressure comprises bonding the second wafer to the first wafer so that the contact element rests on the stop pad. Fluidically coupling comprises defining fluidic passages at an interface between the contact element and the stop pad and opening an access hole through the second wafer in communication with the fluidic passages.

Abstract: A process for manufacturing microelectromechanical devices includes forming a dielectric layer and a structural layer on a substrate of a first semiconductor wafer and forming a first and a second microelectromechanical device in the structural layer. The first and second microelectromechanical devices are sealed respectively in a first chamber and in a second chamber at a first pressure. The first chamber is fluidically coupled to an external environment through the substrate and sealed at a second pressure different from the first pressure. To fluidically couple the first chamber to the outside, there are formed a stop layer between the dielectric layer and the structural layer and a cavity fluidically coupled to the first chamber in the dielectric layer. A channel is formed by etching the substrate in a position corresponding to the cavity and the stop layer, and the etching of the substrate is ended against the stop layer.

Abstract: A system on chip (SoC) includes a CPU, a main bus, and a plurality of subsystems. The SoC also includes an address remapping module coupled between the CPU and the bus. The address remapping module quickly and efficiently changes any memory addresses that need to be changed with the CPU requests a read or write operation associated with the addresses.

Abstract: Disclosed herein is a process flow for forming a MEMS IMU including an accelerometer and a gyroscope each located in a separate sealed cavity maintained at a different pressure. Formation of the MEMS IMU includes the use of a first vHF release to etch a sacrificial layer underneath a structural layer containing the accelerometer and gyroscope and capping the device under formation to set both cavities at a first pressure. The floor of one of the cavities is formed to including a gas permeable layer. Formation further includes forming a chimney underneath the gas permeable layer and then performing a second vHF release to etch through the gas permeable layer and expose the cavity containing the gas permeable layer so that its pressure may be set to be different than that of the other cavity when the chimney is sealed.

Abstract: A voice coil motor (VCM) in a hard disk drive is operated in a discontinuous mode with an alternation of on and off times. A drive current to the VCM is facilitated and countered with a variable voltage across the during the on-times and off-times. The intensity of the drive current is controlled as a function of a Back ElectroMotive Force (BEMF) of the VCM. A method includes sampling during the alternation of on-times and off-times first and second values of the voltage across the VCM. The first value is sampled at a first time in response to the end of the off-time. The second value is sampled at a second time in response to the drive current of the VCM zeroing following the supply of drive current to the VCM being countered during the off-time. The BEMF is calculated as a function of first and second values.

Abstract: A process is provided for manufacturing electronic components with wettable flanks from a substrate in which chips are formed, the chips being separated by cavities, the process including a first step in which an insulating material layer is deposited and then a second step in which a conductive material layer is deposited on the insulating material layer to form wettable flanks. An electronic component with wettable flanks is also provided.

Abstract: A linear voltage regulator includes a first amplification stage configured to produce an error signal at an intermediate node as a function of a difference between a first reference voltage and a regulated output voltage. An intermediate amplification stage amplifies the error signal to produce an amplified error signal. A driver stage produces a drive signal as a function of the amplified error signal. A pass device is controlled by the drive signal to produce the regulated output voltage. A feedback circuit produces a feedback current as a function of a difference between the drive signal and a second reference voltage. The feedback current is the sourced to the intermediate node.

Abstract: A method of manufacturing an electronic device includes the steps of: forming, on a first side of a solid body of Silicon, a first covering layer of SiO2, forming, on the first covering layer, a second covering layer of SiN, and forming, on the second covering layer, a third covering layer of TEOS; forming a passing opening through the first, second and third covering layers. The method includes forming a trench at the portion of the solid body exposed through the opening; grow a sacrificial layer, of the first oxide, within the trench and performing in the order: selectively etching part of the second covering layer, completely removing the sacrificial layer and the third covering layer in one or more contextual etching steps.

Abstract: A method of manufacturing an image sensor comprising the forming of an opening in a substrate, the forming of a conductive pad covering the flanks of the opening and delimiting a gap in the opening, the forming of microlenses in a layer made of a first resin, the layer made of the first resin covering the pad and penetrating into the gap, the forming of a mask made of a second resin on top of and in contact with the layer made of the first resin, the chemical plasma etching of the layer made of the first resin, through the mask, delimiting a block of the first resin in the gap, the deposition of a protective layer on the microlenses and on the block, the removal of the portion of the protective layer covering the block, and the etching of the block.

Abstract: A wearable electronic device detects the breathing of a user based on bone conduction of sounds waves. The wearable electronic device includes an inertial sensor unit. The inertial sensor unit generates sensor data based on bone conduction of sound. The inertial sensor unit generates frequency domain data based on the sensor data. The inertial sensor unit detects breathing of the user by performing a classification process based on the frequency domain data.

Abstract: Described herein is an operational transconductance amplifier (OTA) with a constant current source that provides a constant current to a node. The OTA includes two input pairs of transistors: the first sources variable currents based on feedback and input voltages, while the second sinks variable currents also based on feedback and input voltages. A folded cascode arrangement includes two branches, with one branch including a Monticelli cell. A class-AB output stage is present, with its inputs connected across the Monticelli cell. Additionally, a bias stage mirrors and scales the constant current to generate control voltages. Within the folded cascode branches, compensation transistors are controlled by these control voltages, ensuring that various sourced and sunk variable currents are of equal magnitude, making the OTA input voltage independent.

Abstract: A semiconductor photodetector includes an active region made of a doped semiconductor material of a first conductivity type. The active region is configured to convert a light radiation into charge carriers and to store the charge carriers. At least one repulsion element is positioned within the active region and configured to repel charge carriers stored in the active region.