Abstract: HEMT device comprising: a heterostructure comprising a channel layer and a barrier layer extending, along a first axis, onto the channel layer; a dielectric protection layer of dielectric material, extending along the first axis onto the barrier layer; and a gate region extending along the first axis onto the dielectric protection layer, wherein the dielectric protection layer has, along the first axis, a thickness lower than 10 nm.

Abstract: The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

Abstract: According to an embodiment, a method includes adjusting a reference generator into a first configuration based on a temporary trim value resulting, in a first reference voltage and a first reference current being generated for a first memory. The method further includes performing an integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current. The initial set of data includes a first trim value. The method further includes downloading contents from the first memory into a second memory in response to a successful integrity check after adjusting the reference generator into a second configuration. In the second configuration, the reference generator generates a second reference voltage and a second reference current for the first memory. The reference generator is adjusted by the first trim value in response to a successful integrity check.

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.

Abstract: An electronic frequency mixer includes at least one transistor having a front gate, a back gate, a source, and a drain. The source is coupled to a node of application of a radio frequency input signal. The front gate is coupled to a node of application of a first periodic signal at a first frequency. The back gate is coupled to one of: a node of application of the first periodic signal or a node of application of a second periodic signal at the first frequency.

Abstract: The present disclosure is directed to shock and orientation detection for an electronic device. The shock detection detects shock events, such as an accidental drop of the device, and the orientation detection detects the orientation of the device at the time of the detected shock event. The detected shock event and orientations are stored in non-volatile memory. The shock and orientation detection are implemented in low power hardware without any host intervention, and may be implemented as an always-on feature that executes even when the device is in an off or low power state.

Abstract: A convolutional neural network includes convolution circuitry. The convolution circuitry performs convolution operations on input tensor values. The convolutional neural network includes requantization circuitry that requantizes convolution values output from the convolution circuitry.

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

Abstract: A bidirectional PFC system includes a high-frequency branch with a first transistor connected between an IO node and a high-frequency tap, and a second transistor connected between the high-frequency tap and a reference node, and a low-frequency branch with a first thyristor connected between the IO node and a low-frequency tap, and a second thyristor connected between the low-frequency tap and the reference node. An inductor is connected between the first node and the high-frequency tap. A first capacitor is connected between the first node and the low-frequency tap. The first node and the low-frequency tap are coupled to input terminals. A control circuit generates first and second gate drive signals for the transistors so as to modify an AC signal at the input terminals such that the AC current falls below a holding current of the second thyristor prior to zero crossing of the AC voltage.

Abstract: The disclosure concerns an electronic device comprising, stacked from a first surface to a second surface, a first stack and a second stack of two high electron mobility transistors, referred to as first and second transistor, the first and the second stack each comprising, from an insulating layer, interposed between the first and the second stack, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first and a second set of electrodes, the first and the second set of electrodes being each provided with a source electrode, with a drain electrode, and with a gate electrode which are arranged so that the first and the second transistor form a half-arm of a bridge.

Abstract: A first layer of a resin compatible with a laser direct structuring (LDS) is formed on a substrate and encapsulates a first integrated circuit. The substrate includes a first connection terminal electrically coupled to the first integrated circuit and a second connection terminal covered by the first layer. A first via is formed using LDS, the first via crossing the first layer and forming an electrical connection to the second connection terminal. A second integrated circuit is mounted over the first integrated circuit. A second layer of resin compatible with LDS is formed to encapsulate the second integrated circuit. A second via is formed using LDS, the second via crossing the second layer and forming an electrical connection to the first via.

Abstract: A MEMS accelerometer has a substrate and a sensing mass suspended at a distance from the substrate along an out-of-plane direction. The sensing mass is coupled to the substrate so as to undergo an out-of-plane movement with respect to the substrate, in response to an acceleration along the out-of-plane direction. The MEMS accelerometer also has a damping structure configured to damp an in-plane movement of the sensing mass with respect to the substrate. The damping structure has a plurality of movable fingers integral with the sensing mass and a plurality of fixed fingers integral with the substrate and interdigitated with the movable fingers. The movable fingers and/or the fixed fingers have, along a first in-plane direction transversal to the out-of-plane direction, a variable length.

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

Abstract: A cryptographic operation is protected. The protecting includes performing a matrix transformation operation on a matrix having n rows and n columns, each row forming a respective vector of a first set of ordered vectors. A second set of ordered vectors is generated by shifting values of vectors of the first set of ordered vectors in a first direction, wherein a pitch of a shift applied to a vector of the first set of ordered vectors is based on an order number of the vector of the first set of ordered vectors. A working vector is generated by logically combining vectors of the second set of ordered vectors. A third set of ordered vectors is generated based on the second set of ordered vectors. A fourth set of ordered vectors is generated based on the third set of ordered vectors and the working vector.

Abstract: An electronic device includes—a semiconductor substrate having selection transistors arranged therein and a first interconnection stack including at least one level including first and second insulating layers having conductive tracks and first conductive vias defined therein. The electronic device includes a third insulating layer on the first stack and a second interconnection stack including at least one level including first and second insulating layers. The electronic device includes a plurality of memory cells arranged in the third insulating layer and at least one second conductive via extending through the entire height of the third insulating layer.

Abstract: A device and method of manufacturing a device based on heterostructure, including a work body, is provided having a wafer and an epitaxial multilayer that extends on the wafer along a direction from a front surface of the wafer up to an upper surface. To form an active area, a conduction region of conductive material is formed on the epitaxial multilayer. To form a contact region for biasing the first conduction region: a front trench is formed in the work body starting from the upper surface towards the back surface of the wafer, up to a contact surface; a conductive region is formed inside the front trench, on the contact surface, and in electrical contact with the first conduction region; a back trench is formed in the work body starting from the back surface towards the upper surface up to the contact surface; and a back metallization layer is formed on the back surface of the wafer and inside the back trench, on the contact surface.

Abstract: A first input node and a second input node are coupled to a sensing circuit element. A first transistor of a pair of differential transistors has a current flow path with a first transistor node coupled to the first input node to receive a current sensing signal and a second transistor node. A second transistor of the pair of differential transistors has a current flow path with a third transistor node coupled to the second input node to receive a current sensing signal and a fourth transistor node. An auxiliary amplifier circuit has a first auxiliary input node coupled to the second transistor node and a second auxiliary input node coupled to the fourth transistor node. An output node of the auxiliary amplifier circuit generates a control signal applied to a common control node of the pair of differential transistors.

Abstract: An electronic device, such as a smart card, includes a first secure element configured to implement a transaction in response to received data, and a second secure element configured to receive the same data as the first secure element and perform an operation which can control another electronic circuit.

Abstract: A foldable electronic device includes a first lid and a second lid rotatably coupled together by a hinge. A first inertial measurement unit (IMU) is implemented in the first lid and generates first sensor data. A second IMU is implemented in the second lid and generates second sensor data. A sensor processing unit detects the rotation angle between the first and second lids and generates rotated second sensor data by adjusting the second sensor data based on the rotation angle. The sensor processing unit generates combined sensor data by combining the first sensor data with the rotated second sensor data. The combined sensor data is more accurate than either the first sensor data or the second sensor data.