Patents Assigned to STMicroelectronics International N.V.
  • Publication number: 20190334530
    Abstract: A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin GUPTA, Kapil Kumar TYAGI
  • Publication number: 20190331733
    Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan SRINIVASAN, Manish SHARMA
  • Patent number: 10461636
    Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: October 29, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Publication number: 20190326911
    Abstract: A level shifting circuit receives a first input signal and complement of the first input signal as inputs and generates a level shifted first output signal and complement of the first output signal as outputs. The level shifting circuit includes a number of transistors that support body biasing. One set of body bias signals applied to certain ones of those transistors is generated as a function of the logical combination of the first input signal and the first output signal. Another set of body bias signals applied to certain other ones of those transistors is generated as a function of the logical combination of the complement of the first input signal and the complement of the first output signal. The conditional body bias applied to the transistors of the level shifting circuit makes the circuit operational for level shift at very low supply voltage levels.
    Type: Application
    Filed: June 4, 2019
    Publication date: October 24, 2019
    Applicant: STMicroelectronics International N.V.
    Inventor: Ravinder KUMAR
  • Patent number: 10454466
    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Manoj Kumar Kumar Tiwari, Saiyid Mohammad Irshad Rizvi
  • Patent number: 10454532
    Abstract: When communicating using active load modulation in a Radio Frequency Identification (RFID) system, a carrier signal having a carrier frequency is received from a reader device. In response, a modulated signal is generated and a burst of a sending signal is transmitted. The sending signal is decayed at the end of the burst.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: October 22, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Kosta Kovacic, Albin Pevec
  • Publication number: 20190319453
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Ghislain TROUSSIER, Jean JIMENEZ, Malathi KAR
  • Publication number: 20190319454
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan SITHANANDAM, Divya AGARWAL, Jean JIMENEZ, Malathi KAR
  • Publication number: 20190317851
    Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Om RANJAN, Riccardo GEMELLI, Abhishek GUPTA
  • Publication number: 20190312575
    Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.
    Type: Application
    Filed: January 22, 2019
    Publication date: October 10, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Manoj Kumar Kumar TIWARI, Saiyid Mohammad Irshad RIZVI
  • Publication number: 20190296800
    Abstract: An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Kosta KOVACIC, Albin PEVEC, Maksimiljan STIGLIC
  • Patent number: 10425173
    Abstract: A method for a phase calibration in a frontend circuit of a near field communication (NFC) tag device is disclosed. An active load modulation signal is generated with a preconfigured value of a phase difference with respect to a reference signal of an NFC signal generator device. An amplitude of a test signal present at an antenna of the NFC tag device is measured. The test signal results from overlaying of the reference signal with the active load modulation signal. The following steps are repeated: modifying the value of the phase difference, providing the active load modulation signal with the modified value of the phase difference, measuring an amplitude of the test signal and comparing the measured amplitude with the previously measured amplitude until the measured amplitude fulfills a predefined condition. The value of the phase difference corresponding to the previously measured amplitude is stored.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 24, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Nicolas Cordier
  • Publication number: 20190288693
    Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
    Type: Application
    Filed: March 19, 2018
    Publication date: September 19, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Jeet Narayan Tiwari
  • Patent number: 10417364
    Abstract: Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 17, 2019
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10418095
    Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node. A bias circuit applies a biasing voltage to the gate terminal of the n-channel pull-down transistor that is modulated responsive to process, voltage and temperature conditions in order to provide controlled word line underdrive.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: September 17, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Abhishek Pathak
  • Publication number: 20190279707
    Abstract: A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 12, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Abhishek PATHAK, Tanmoy ROY, Shishir KUMAR
  • Patent number: 10402527
    Abstract: Embodiments are directed towards a reconfigurable stream switch formed in an integrated circuit. The stream switch includes a plurality of output ports, a plurality of input ports, and a plurality of selection circuits. The output ports each have an output port architectural composition, and each is arranged to unidirectionally pass output data and output control information. The input ports each have an input port architectural composition, and each is arranged to unidirectionally receive first input data and first input control information. Each one of the selection circuits is coupled to an associated one of the output ports. Each selection circuit is further coupled to all of the input ports such that each selection circuit is arranged to reconfigurably couple its associated output port to no more than one input port at any given time.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 3, 2019
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10405384
    Abstract: A circuit includes a voltage converter converting source voltage to supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between first and second node nodes. Feedback circuitry couples the second node to the feedback node when a voltage at the second node exceeds a first overvoltage, in a first mode of operation. The feedback circuitry couples the second node to the feedback node when the voltage at the second node exceeds a second overvoltage less than the first overvoltage, in a second mode of operation. Impedance circuitry is coupled between the first node and a third node and generates an auxiliary supply voltage and an auxiliary ground voltage when the circuit is in both the first and second modes, the auxiliary supply voltage being less than the supply voltage in both the first and second modes.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Akshat Jain, Ranajay Mallik
  • Patent number: 10404278
    Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Rakesh Malik
  • Patent number: 10393804
    Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 27, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Nimit Endlay, Balwinder Singh Soni