Patents Assigned to STMicroelectronics International N.V.
  • Publication number: 20240045458
    Abstract: Provided are techniques for detecting a short circuit fault at an output of a regulator and protecting the regulator from the short circuit fault. An error amplifier receives a reference voltage and a feedback voltage and compares comparing the reference voltage with the feedback voltage for driving a power transistor of the regulator. A modification stage compares an output voltage of the voltage regulator with a fault reference voltage and in response to determining that the output voltage of the voltage regulator is less than the fault reference voltage, drives the power transistor using an internal node of the error amplifier by changing states of a first switch and a second switch and supplies the reference voltage to both the first and second inputs of the error amplifier by changing states of a third switch and a fourth switch.
    Type: Application
    Filed: July 21, 2023
    Publication date: February 8, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Zubair KHAN, Sandeep KAUSHIK
  • Patent number: 11892505
    Abstract: A processing system includes: main and shadow processing cores configured to operate in lockstep based on a core clock. The main processing core includes a main processing core and a main debug circuit. The shadow processing core includes a shadow functional core and a shadow debug circuit. A redundancy checker circuit is configured to assert an alarm signal when a discrepancy between outputs from the main and shadow functional cores is detected. A debug bus synchronizer circuit is configured to receive input debug data in synchrony with a debug clock, and provide synchronized debug data in synchrony with the core clock to a debug bus based on the input debug data, where the main and shadow debug circuits are configured to receive the synchronized debug data in synchrony with the core clock from the debug bus, and where the debug clock is asynchronous with respect to the core clock.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: February 6, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Avneep Kumar Goyal, Anubhav Arora
  • Publication number: 20240039545
    Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.
    Type: Application
    Filed: July 7, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Rupesh SINGH, Ankur BAL
  • Publication number: 20240039537
    Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.
    Type: Application
    Filed: July 20, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Manoj KUMAR, Paras GARG, Saiyid Mohammad Irshad RIZVI
  • Patent number: 11885849
    Abstract: A method can be used for supervising the operation of a machine powered with electric current. The method includes operating the machine in a normal operation mode, repeatedly performing a learning phase for learning the normal operation machine of the machine to create a knowledge base, autonomously switching from the learning phase into a supervision phase when the knowledge base is considered to have been created, and repeatedly performing the supervision phase.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 30, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: He Huang, Francois De Grimaudet De Rochebouet
  • Patent number: 11889675
    Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: January 30, 2024
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tushar Sharma, Tanmoy Roy, Shishir Kumar
  • Patent number: 11881280
    Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: January 23, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Shivam Kalla, Vikas Rana
  • Patent number: 11880759
    Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: January 23, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Giuseppe Desoli, Carmine Cappetta, Thomas Boesch, Surinder Pal Singh, Saumya Suneja
  • Publication number: 20240012871
    Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Antonio DE VITA, Thomas BOESCH, Giuseppe DESOLI
  • Patent number: 11868197
    Abstract: A learning method detects anomalies and is implemented on a microcontroller including at least one memory, the microcontroller being configured to receive data sets coming from at least one sensor, the memory being configured to store a maximum number of categories, a category including at least a signature and an occurrence.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: January 9, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Francois De Rochebouet, He Huang
  • Patent number: 11863066
    Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 2, 2024
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Vikas Rana, Marco Pasotti, Fabio De Santis
  • Patent number: 11860993
    Abstract: A method of operating an electronic device includes generating scramble control codes. The scramble codes are generated by generating a random number, shifting the random number to produce a shifted random number, generating control signals by selecting different subsets of the shifted random number, and generating scramble control words by selecting different subsets of the random number based upon the control signals. The method further includes receiving a password comprised of sub-words and scrambling those sub-words according to the scramble control codes, retrieving a verification word comprised of sub-words and scrambling those sub-words according to the scramble control codes, and comparing the scrambled sub-words of the password to the scrambled sub-words of the verification word to thereby authenticate an external device that provided the password.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 2, 2024
    Assignee: STMicroelectronics International N.V.
    Inventor: Dhulipalla Phaneendra Kumar
  • Publication number: 20230421101
    Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Anand KUMAR, Nitin JAIN
  • Publication number: 20230418559
    Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1√óN kernels, where N is an integer greater than or equal to 1.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Michele ROSSI, Thomas BOESCH, Giuseppe DESOLI
  • Patent number: 11855527
    Abstract: A PFC correction circuit includes first, second, and third phase inputs coupled to three-phase power mains, with a three-phase full-wave rectifying bridge connected to an input node. First, second, and third boost inductors are respectively connected between first, second, and third phase inputs and first, second, and third taps of the three-phase full-wave rectifying bridge. A boost switch is connected between the input node and ground, and a boost diode is connected between the input node and an output node. A multiplier input driver generates a single-phase input signal as a replica of a signal at the three-phase power mains after rectification. A single-phase power factor controller generates a PWM signal from the single-phase input signal. A gate driver generates a gate drive signal from the PWM signal. The boost switch is operated by the gate drive signal.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: December 26, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Ranajay Mallik, Akshat Jain
  • Patent number: 11855654
    Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: December 26, 2023
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V.
    Inventors: Nicolas Moeneclaey, Sri Ram Gupta
  • Publication number: 20230410892
    Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
    Type: Application
    Filed: April 20, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Harsh RAWAT, Manuj AYODHYAWASI
  • Publication number: 20230412155
    Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.
    Type: Application
    Filed: May 25, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Nitin JAIN, Anand KUMAR, Kallol CHATTERJEE
  • Publication number: 20230410862
    Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.
    Type: Application
    Filed: April 19, 2023
    Publication date: December 21, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
  • Patent number: 11848672
    Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: December 19, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Sandeep Jain, Jeena Mary George