Abstract: A Phase Change Memory (PCM) device includes sets of cells in which a binary logic level is written by a write operation. Each cell is included in a respective set of cells in the sets of cells. The write operation includes: performing write verify operations on the cells to identify an actual logic level stored in the cells; checking if the identified actual logic level matches a certain the binary logic level; in response to the checking determining that in at least one cell the actual logic level fails to match the binary logic level, correcting the actual logic level to match the binary logic level by performing: a set write operation in case the binary logic level is a high logic level, or a reset write operation in case the binary logic level is a low logic level.

Abstract: A circuit, a circuit for generating adaptive SET pulse currents for phase-change memory (PCM) cells is disclosed. The circuit includes a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current with a programmable profile, the programmable profile comprising a constant current phase at a predefined set current, a first ramping-down phase from the predefined set current to a minimum cutoff current, a second ramping-down phase from the minimum cutoff current to zero, and a zero-current phase, wherein the constant current phase for each IDAC starts in response to the other IDAC starting the second ramping-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate the adaptive SET pulse currents.

Abstract: A method for transmission of monochrome video data of a monochromatic image, wherein three different source monochromatic pixels are encoded by a transmitting device into one compressed three-color pixel; the compressed three-color pixel are transmitted by the transmitting device. The transmitted compressed three-color pixel are received at a receiving device; and the compressed three-color pixel decoding are decoded by the receiving device into three different sink monochromatic pixels. The transmitting device acquires the three different source monochromatic pixels, extracts a single-color value from each of the three different source monochromatic pixels, and generates the compressed three-color pixel using the single-color values extracted from the three different source monochromatic pixels.

Abstract: A galvanically isolated current sensor for power converters is disclosed. The sensor includes a package housing a first integrated circuit (IC), a light emitting layer, an optical waveguide, a photosensing layer, and a second IC. The light emitting layer emits light proportional to a reference current. The optical waveguide modulates the light based on a magnetic field generated by the current to be sensed. The photosensing layer generates a photocurrent representative of the modulated light's intensity. The second IC outputs a sense current based on the photocurrent. The optical waveguide includes polarizers and a Faraday rotator material to effectuate the modulation. Different embodiments of control circuitry for processing the sense current are described, including a flash ADC-based system, a voltage-controlled oscillator with a high-speed counter, and a current-controlled delay line with a low-speed counter.

Abstract: Provided is a circuit for managing a first clock signal clocking a timer adapted to being controlled by a processor clocked by a second clock signal. When the processor is off, the first clock signal is equal to a third clock signal having a frequency lower than the frequency of the second clock signal. When the processor is on, the first clock signal is equal to a fourth signal having a rising edge at each rising edge of the second clock signal directly following a rising edge of the third clock signal.

Abstract: The present disclosure is directed to a stacked assembly including a polycrystalline Silicon Carbide (SiC) substrate on which a monocrystalline SiC layer and one or more epitaxial layers are stacked. The one or more epitaxial layers are completely separated from the polycrystalline SiC substrate by the monocrystalline layer, which is stacked on the polycrystalline SiC substrate such that the monocrystalline SiC layer is between the one or more epitaxial layers and a respective surface of the polycrystalline SiC substrate. The present disclosure is further directed to one or more embodiments of methods of manufacturing one or more embodiments of the stacked assemblies.

Abstract: A radio frequency signal amplifier includes an input differential transistor pair and an output differential transistor pair. First and second capacitive elements are arranged, respectively, between control terminals and conduction terminals of transistors of the input differential transistor pair. Third and fourth capacitive elements are arranged, respectively, between control terminals and conduction terminals of transistors of the output differential transistor pair. These capacitive elements may be formed by transistors or capacitors. An amplifier input is coupled through a transformer to the control terminals of the transistors of the input differential transistor pair. An amplifier output is coupled to through magnetically coupled coils to further conduction terminals of the transistors of the output differential transistor pair.

Abstract: A wafer includes integrated circuit areas, where each integrated circuit area has at least one conductive die pad. A passivation layer is provided over the conductive die pads. A die pad opening is formed extending through the passivation layer at each die pad. Use a jet printing process, a dot of conductive ink is deposited at each die pad opening to form a die pad protection layer covering an upper surface of each conductive die pad. A film layer covers the passivation layer and the die pad protection layer at each die pad. Using a laser drilling process, a via opening if formed extending through the film layer at each die pad to reach the die pad protection layer. The die pad protection layer protects the die pad during the laser drilling.

Abstract: The control device for a regulator with a switching circuit. The device includes an oscillator that provides a clock signal having a switching period; a circuit that provides a comparison signal indicative of a comparison between an input voltage and an output voltage; and a circuit that generates a signal to drive the switches of the switching circuit as a function of an error between the output voltage and a nominal voltage. The device controls, within the switching period, a first phase having a current path between the input and output node through the inductive element; a second phase having a current path between the input and common node through the inductive element; and a third phase having a current path between the output and common node through the inductive element. The sequence of the first, second, and third phases is a function of the comparison signal.

Abstract: The present disclosure relates to a pulse width modulation circuit of a switched-mode power supply formed in and on a monolithic semiconductor substrate with a face coated with a gallium nitride layer, said circuit being adapted to control a power transistor of said switched-mode power supply.

Abstract: The present disclosure relates to an image sensor comprising an array of pixels arranged in first rows and in first columns. The pixels are arranged in groups of N*N pixels, with N an integer equal to or higher than 2. In each group, the pixels of the group are distributed into one or more sub-groups of a plurality of pixels. Each pixel comprises: a photosensitive element, a first node coupled to the photosensitive element, a second node common to all pixels of a same sub-group, and coupled to a first potential, a first transistor coupling the first and second nodes to each other, a second source-follower transistor having a gate connected to the first node, and a third transistor coupling the source of the third transistor to a reading line.

Abstract: A method for operating an electronic device. The method includes detecting a plurality of touch inputs for a plurality of frames on a touchscreen of the device. The plurality of touch inputs includes a first touch input and a second touch input. The first touch input is immediately adjacent to the second touch input from amongst the plurality of touch inputs and the plurality of frames comprising a current frame and a preceding frame. The method further includes determining a distance between the first and the second touch inputs on the current frame, determining a speed between the first touch input on the current frame and the first touch input on the preceding frame, and merging, for the current frame, the first touch input with the second touch input into a single touch input based on the determined distance and the determined speed.

Abstract: A device for limiting a current, includes a differential amplifier configured to equalize voltages across a power transistor and a sense transistor and a regulation circuit of an output current of the device for limiting a current. The regulation circuit includes a transconductance amplifier configured to limit the output current when an output electric potential of the differential amplifier is higher than or equal to a reference electric potential proportional to a reference current the value of which is equal to ILIMIT/(N.M), with ILIMIT corresponding to a current limit value, N corresponding to an aspect ratio between the power transistor and the sense transistor, and M corresponding to an aspect ratio between transistors of a current mirror coupled to the sense transistor.

Abstract: The present description relates to a method of manufacturing a silicon-on-insulator substrate comprising the successive steps of: a) formation of a silicon-germanium layer on an upper surface of a silicon substrate; b) formation of a silicon layer on an upper surface of the silicon-germanium layer; c) formation of at least one opening crossing the silicon layer and emerging into the silicon-germanium layer; d) selective removal of at least part of the silicon-germanium layer through the opening to create a cavity between the silicon substrate and the silicon layer; and e) filling the cavity through the opening with an insulating material.

Abstract: An SPI link includes three wires between a master circuit and a slave circuit. Data are transferred in packets, each packet including a payload and a header specifying the length of the payload of the packet. During a data transfer between the master and slave circuits, the master circuit defines a number N of bytes to be transferred. The master circuit then determines, after a transfer of N bytes from the master circuit to the slave circuit and a transfer of N bytes from the slave circuit to the master circuit, a number of bytes remaining to be transferred from the slave circuit to the master circuit. This determination is made by the master circuit by reading a value of a length of the payload included in the header of a data packet transferred from the slave circuit to the master circuit.

Abstract: A DC-DC power converter includes a continuous-time comparator that monitors an input voltage and an output voltage to automatically control a preselector core. The comparator generates bias conditions based on the actual voltage differential between the input voltage and the output voltage, eliminating the need for discrete logic control. When the input voltage exceeds the output voltage, the circuit configures itself to enable charging of the output voltage through a controlled current path. When the output voltage exceeds the input voltage, the circuit reconfigures to enable current recirculation through the preselector core. The continuous-time comparison eliminates static current consumption during reset phases and provides immediate response to voltage differentials without complex timing or control logic. This architecture results in a simple, efficient voltage converter well suited for applications desiring minimal control overhead and responsive voltage regulation.

Abstract: A device includes a plurality of hardware accelerator islands. The accelerator islands have a plurality of processing elements, a plurality of streaming engines, and a stream switch coupled to the plurality of processing elements and to the plurality of streaming engines. The stream switch streams data between the plurality of processing elements of the accelerator island, and between the plurality of streaming engines of the accelerator island and the plurality of processing elements of the accelerator island. Unidirectional stream switch connections (SSCONNs) are coupled between pairs of stream switches of the plurality of accelerator islands. The stream switches of the plurality of hardware accelerator islands and the SSCONNs form a run-time reconfigurable interconnection mesh between the plurality of processing elements of the plurality of hardware accelerator islands.

Abstract: A method comprising measuring raw data by simultaneously driving a plurality of channels of a foldable device, collecting the raw data from a first channel on a first portion and a second channel on a second portion of the device, the first channel being positioned opposite from the second channel relative to a folding axis of the foldable device, determining a distance between the first channel and the second channel based on the collected raw data, generating a baseline capacitance based on the distance between the first channel and the second channel, filtering the generated baseline capacitance, calculating strength data based on the filtered baseline capacitance and the collected raw data; and determining a folding state based on the calculated strength data.

Abstract: A method of operating a time-of-flight (ToF) ranging system includes: receiving a histogram that includes a cross-talk signal generated by reflected light pulses from a cover glass of the ToF ranging system; finding, in a first region of the histogram, a first rising edge having a gradient that is larger than a threshold or is a maximum gradient in the first region, where the first rising edge is in a first histogram bin having a first value; determining a second value of a second histogram bin in the first region, where the first histogram bin precedes the second histogram bin by a pre-determined distance; estimating a ratio between the first region of the histogram and a pre-stored light pulse shape based on the first value and the second value; scaling the pre-stored light pulse shape with the estimated ratio; and subtracting the scaled pre-stored light pulse shape from the histogram.

Abstract: The present disclosure relates to a short-circuit detection device in a direct current circuit, including a voltage source, a bus including at least two conducting elements each coupled to either one of the terminals of the voltage source, first and second thyristors coupled to the voltage source and to the bus, and at least one capacitive element forming a storage capacitor, whose electrodes are each coupled to either one of the conducting elements of the bus, wherein the short-circuit detection device includes at least one control circuit configured to control the biasing and the modes of operation of the first and second thyristors such that a short circuit detection phase is implemented before a pre-charge of the storage capacitor.