Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

Abstract: A process flow for forming a Wafer-Level Chip Scale Package (WLCSP) provides protection against copper-ion migration while enabling high-density redistribution layers. The process includes forming first and second passivation layers with redistribution layer (RDL) conductors between them. Embodiments herein utilize different barrier structures between adjacent RDL conductors to inhibit copper-ion migration. In a first embodiment, a groove structure in the first passivation layer creates an extended pathway between RDL conductors. A second embodiment utilizes an opening in the first passivation layer to achieve similar protection. A third embodiment utilizes a through-hole structure penetrating multiple passivation layers, which serves as a migration barrier and accommodates additional RDL routing.

Abstract: Apparatuses, systems, and methods to balance flying capacitors in high power multi-level buck or boost converters for renewable and solar maximum power point tracking (MPPT) inverter applications are provided. An exemplary method includes initializing at least a multi-level converter circuitry and an isolated secondary converter circuitry, wherein the multi-level converter circuitry includes at least a flying capacitor, and wherein the isolated secondary converter circuitry is configured to charge the flying capacitor in accordance with a default operation state in response to initialization; determining that a voltage across the flying capacitor satisfies a threshold; and causing the isolated secondary converter circuitry to switch from the default operation state to an inactive state based at least in part on the voltage satisfying the threshold.

Abstract: According to an embodiment, a method is proposed that includes sensing a reverse current through a main switch of an active clamp flyback (ACF) converter. The ACF converter includes a flyback transformer and an auxiliary switch. The method further includes determining whether a sense voltage corresponding to the reverse current exceeds a threshold; decreasing a duration for the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration that the auxiliary switch is activated; increasing the duration by a second incremental time interval greater than the first incremental time interval, the increasing being in response to the reverse current not exceeding the threshold; and activating the auxiliary switch for the duration to achieve zero voltage switching (ZVS).

Abstract: A cryptographic operation is protected. The protecting includes performing a matrix transformation operation on a matrix having n rows and n columns, each row forming a respective vector of a first set of ordered vectors. A second set of ordered vectors is generated by shifting values of vectors of the first set of ordered vectors in a first direction, wherein a pitch of a shift applied to a vector of the first set of ordered vectors is based on an order number of the vector of the first set of ordered vectors. A working vector is generated by logically combining vectors of the second set of ordered vectors. A third set of ordered vectors is generated based on the second set of ordered vectors. A fourth set of ordered vectors is generated based on the third set of ordered vectors and the working vector.

Abstract: An example electronic system utilizing an optical ranging, proximity, and/or image sensor configured with retroreflective mechanisms to reduce unwanted optical noise at an optical radiation receiver are provided. The example ranging, proximity, and/or image sensor is configured to include a housing cap having a transmission opening and a receiving opening. The example sensor may further include an optical radiation source positioned to direct ranging optical radiation through the transmission opening toward a target object. An optical radiation receiver is positioned to receive ranging optical radiation reflected off the target object through the receiving opening. A retroreflective mechanism implemented on a surface of the housing cap directs unwanted optical noise back towards an unwanted optical noise source and away from the optical radiation receiver. Properties of the target object may be determined based on one or more properties of the ranging optical radiation received at optical radiation receiver.

Abstract: A hardware accelerator includes processing elements of a neural network, each processing element having a memory; a stream switch; stream engines coupled to functional circuits via the stream switch, wherein the stream engines, in operation, generate data streaming requests to stream data to and from functional circuits of the plurality of functional circuits; a first system bus interface coupled to the stream engines; a second system bus interface coupled to the processing elements; and mode control circuitry, which, in operation, sets respective modes of operation for the plurality of processing elements. The modes of operation include: a compute mode of operation in which the processing element performs computing operations using the memory associated with the processing element; and a memory mode of operation in which the memory associated with the processing element performs memory operations, bypassing the stream switch, via the second system bus interface.

Abstract: A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.

Abstract: The present description concerns a bus error management method, wherein one or a plurality of first characteristics of a first write transaction intended for a functional unit and transiting through a bridge, are stored, and wherein in the presence of a bus error sent by the functional unit: one or a plurality of second characteristics linked to said error are stored; the bridge generates a first interrupt that it transmits with said first and second characteristics to a management unit; and the management unit generates at least one second interrupt intended for a processing unit as a function of the first and/or second characteristics.

Abstract: A microelectromechanical accelerometer includes a microstructure, having sensing terminals and driving terminals distinct from the sensing terminals, a supporting body and a movable mass, coupled to the supporting body so as to be able to oscillate according to a sensing axis with respect to a rest position, and a control unit coupled to the microstructure so as to form a force feedback loop configured to maintain the movable mass in the rest position. The movable mass includes a sensing structure and a driving structure, respectively coupled to the sensing terminals and to the driving terminals through capacitive couplings variable as a function of displacements of the movable mass from the rest position. The sensing structure and the driving structure are electrically insulated and rigidly coupled with each other.

Abstract: A first semiconductor die is arranged at a die pad of a substrate including electrically conductive leads arranged sidewise of the die pad. An electrically conductive clip extends bridge-like between the first semiconductor die and at least one lead out of the electrically conductive leads to provide electrical coupling therebetween. The electrically conductive clip is applied onto the first semiconductor die with a first surface of the electrically conductive clip facing the first semiconductor die. An electrically insulating layer is present at a second surface of the electrically conductive clip opposite the first surface. A second semiconductor die is arranged on the electrically insulating layer. Electrical insulation of the second semiconductor die from the electrically conductive clip is facilitated by the electrically insulating layer formed at the second surface of the electrically conductive clip.

Abstract: A semiconductor die has a die-attachment surface in contact with die-attach material provided at a die mounting region of a surface of a substrate. Die-attach material is provided at a first portion of at least one recess formed in the surface of the substrate. The first portion of the at least one recess lies within the mounting region and the at least one recess includes second portions lying adjacent the mounting region. The second portions of at least one recess facilitate accumulation of die-attach material oozing out of the first portion of at least one recess in response to the semiconductor die being arranged onto the die-attach material provided at the mounting region.

Abstract: A semiconductor electronic device has a semiconductor body of a first conductivity type, that has a front surface and a back surface at a distance from the front surface along a first direction, and a lateral edge; an active area that accommodates, in use, a conductive channel of the electronic device; and an edge termination structure alongside the active area, between the active area and the lateral edge along a second direction transversal to the first direction.

Abstract: An array of piezoelectric micromachined ultrasound transducers (PMUTs) includes a substrate having first and second cavities buried therein. A first piezoelectric stack is carried by the substrate and at least partially overlays the first cavity. A second piezoelectric stack is carried by the substrate and at least partially overlays the second cavity. A thickness of the substrate between the second cavity and the second piezoelectric stack forms a membrane. Circuitry operates the second piezoelectric stack so as to vibrate the membrane to generate a pulse of ultrasound and to immediately subsequently operate the first piezoelectric stack to cause deformation of the second cavity which results in an increase in a resonant frequency of the membrane.

Abstract: A hardware accelerator includes a stream switch, a programmable component and multi-context control circuitry. The stream switch streams a data stream to the programmable component and to the multi-context control circuitry. The multi-context control circuitry, in a configured context mode of operation, counts valid data transactions of the data stream streamed to the programmable component, and controls a sequence of processing operations to be performed on the data of the data stream by the programmable component based on the counting of the valid data transactions of the data stream and on stored configured-context mode configuration information. The multi-context control circuitry, in a hybrid context mode of operation, monitors the data stream to read embedded context tags, and controls a sequence of processing operations to be performed on the data based on the embedded context tags, on the counting of the valid data transactions, and stored hybrid-context mode configuration information.

Abstract: According to one aspect, a microcontroller is proposed including a control circuit of a three-level converter. The converter includes at least one phase branch including an upper transistor, an upper intermediate transistor, a lower intermediate transistor and a lower transistor disposed in series between two terminals of a power source. The control circuit includes a shutdown management circuit configured to keep in a conducting state the upper intermediate transistor and the lower intermediate transistor before making them non-conducting when an event requiring shutdown of the converter occurs.

Abstract: A stream-triggered multi-thread accelerator includes a data streaming interface, a memory, vector processing circuitry and scheduling circuitry. The data streaming interface, in operation, receives and transmits data streams of a plurality of data streaming channels. The memory, in operation, stores a plurality of instruction threads. The plurality of instruction threads include wait-for-trigger instructions specifying streaming data trigger thresholds, and instructions having data streaming channels of the plurality of data streaming channels as operands. The vector processing circuitry is coupled to the memory and to the data streaming interface. The vector processing circuitry, in operation, executes instruction threads of the plurality of instruction threads. The scheduling circuitry, in operation, schedules execution of instruction threads of the plurality of instruction threads by the vector processing circuitry based on the streaming data trigger thresholds of the wait-for-trigger instructions.

Abstract: A memory array includes memory cells arranged in a matrix with cell rows coupled to word lines and cell columns coupled to output bit lines. A control circuit maps a first group of memory cells to a first in-memory compute operation producing computation output signals on first output bit lines from a first matrix vector multiplication of a first input vector with a first group of computation weights stored in the first group of memory cells and maps a second group of memory cells to a second in-memory compute operation producing computation output signals on second output bit lines, different from the first output bit lines, from a second matrix vector multiplication of a second input vector, different from the first input vector, with a second group of computation weights stored in the second group of memory cells. The first and second in-memory compute operations are substantially simultaneously executed.

Abstract: Disclosed herein is a dual low-dropout (LDO) regulator system including two LDO regulators sharing a single operational amplifier, configured for switchover operation. The first LDO regulator is supplied from a high-voltage input, while the second is supplied from from a regulated output voltage. Both regulators remain partially active during operation, with the second LDO regulator taking over a majority of the load current when the regulated output voltage reaches sufficient levels. This prevents voltage dips and oscillations commonly seen in traditional two-LDO systems during switchover.

Abstract: An integrated circuit includes a reference voltage generator configured to generate a bandgap reference voltage. The integrated circuit includes a bipolar transistor configured to provide a base-emitter voltage as a voltage complimentary to absolute temperature (VCTAT) to the reference voltage generator. The integrated circuit includes a bias current generation circuit configured to generate and drive a bias current through the bipolar transistor. The bias current generation circuit utilizes pairs of resistors in two current paths to generate the bias current in manner that compensates for the ? parameter of a bipolar transistor while being substantially immune to mismatches.