Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

Abstract: A bipolar transistor includes: a semiconductor stack having a three-dimensional wire shape successively comprising a collector portion, a base portion and an emitter portion. A lower insulating layer at least partly surrounds and is in contact with a lateral edge of the collector portion. An intermediate doped layer at least partly surrounds and is in contact with a lateral edge of the base portion. An upper insulating portion at least partly surrounds and is in contact with a lateral edge of the emitter portion.

Abstract: A MEMS device includes a semiconductor body having top and bottom surfaces, opposite to each other along a first axis. The top surface has a first zone and a second zone, lateral to each other orthogonally to the first axis. A first conductive region extends on the first zone of the top surface and has a respective top surface that is opposite to the semiconductor body along the first axis and is made of platinum. A passivation region made of silicon oxynitride (SiON), silicon nitride (SiN), or silicon oxide (SiO)includes a first portion, extending on the second zone of the top surface of the semiconductor body, and a second portion, extending on the first conductive region. The first portion has a first thickness along the first axis and the second portion has a second thickness along the first axis, the second thickness greater than the first thickness.

Abstract: An encapsulation of electrically insulating encapsulation material, having opposite first and second surfaces, embeds at least one semiconductor die having an active surface at the first surface of the encapsulation and a back surface opposite said active surface covered by electrically insulating encapsulation material. Vias extending from the second surface towards the back surface of the at least one semiconductor die are formed by laser beam energy. Thermally conductive material grown at the second surface of encapsulation produces a heat dissipation formation for the at least one semiconductor die. The heat dissipation formation includes a thermally conductive layer on the second surface of the encapsulation thermally coupled to the at least one semiconductor die via thermally conductive material grown at the vias formed in the second surface of the encapsulation.

Abstract: Electrically conductive pillars of a semiconductor die are mounted onto a substrate. The substrate and semiconductor die mounted thereon are encapsulated in an encapsulation of electrically insulating material. The encapsulation of electrically insulating material has a first surface at the substrate and a second surface opposite the first surface. Electrically insulating material is removed from the second surface of the encapsulation to form an opening which exposes a back surface of the semiconductor die opposite said active surface. A thermally conductive layer is provided in the opening in heat transfer relationship with the exposed back surface of the semiconductor die to provide a heat dissipation structure.

Abstract: A blood pressure monitoring device includes a patch including two inertial measurement units placed adjacent to the skin of a user. The blood pressure monitoring device is configured to transmit sensor data to an electronic device. The electronic device is configured to guide the user through a series of positional adjustments to align the two inertial measurement units along an artery of the user based on the sensor data.

Abstract: An isolated CLLC DC-DC converter includes transistors arranged in full-bridge configurations on primary and secondary sides, with resonant components and a transformer providing isolation between sides. Driving circuitry monitors switching node voltages to determine zero voltage and zero current conditions for improving switching efficiency. The converter adapts its control strategy based on the relationship between switching frequency and resonant frequency. When switching frequency exceeds resonant frequency, synchronous rectification transistors are turned off based on time delay signals. When switching frequency is less than resonant frequency, synchronous rectification transistors are turned off based on comparator signals at zero current detection points. The converter operates bidirectionally, with a mode selection enabling the same hardware to function in both charge and discharge modes by swapping primary driving and synchronous rectification functions between sides.

Abstract: A substrate has a front surface with front connection pads. An integrated circuit die, having a front surface with die connection pads and rear surface, is mounted to the substrate in a flip chip orientation with the front surface of the integrated circuit die facing the front surface of the substrate. The die connection pads are electrically connected to the front connection pads. A thermally conductive cap is mounted to the substrate to enclose the integrated circuit die. A compliant heat spreader is positioned between the rear surface of the integrated circuit die and an inside surface of the thermally conductive cap. The compliant heat spreader is made of a porous metal foam material layer having pores which contain a thermal interface material.

Abstract: Provided is a double-sided cooled (DSC) package. The package includes a first structure including a first interconnection layer, a first dielectric layer formed on the first interconnection layer, a second interconnection layer formed on the first dielectric layer and a first substrate formed on the second interconnection layer. The package includes a second structure including a third interconnection layer, a second dielectric layer formed on the third interconnection layer and a fourth interconnection layer formed on the second dielectric layer. The package includes a first spacer element that contacts the first substrate and the fourth interconnection layer and a second spacer element that contacts the second interconnection layer and the fourth interconnection layer.

Abstract: The present description concerns an integrated circuit comprising at least two secure circuits having similar functions but respecting or complying with different security schemes.

Abstract: A power management integrated circuit (PMIC) for AMOLED displays includes a negative voltage generator using an adaptive constant-on-time (COT) ripple-based inverting buck-boost architecture. The circuit features a ripple reconstructor that addresses load regulation issues by regenerating attenuated ripple signals from the switching node. The ripple reconstructor utilizes an error amplifier functions as an integrator at low frequencies for accurate DC regulation, and operates as an AC buffer at higher frequencies to preserve ripple information. An adaptive TON control circuit dynamically adjusts the high-side power transistor on-time based on input and output voltage differentials, maintaining pseudo-fixed switching frequency regardless of operating conditions.

Abstract: An example apparatus and optical emission device for preventing the transmission of electromagnetic radiation to and from targeted electrical components of an electronic device are provided. The example apparatus may include an optical emissions component electrically connected to a target electrical portion and configured to generate an optical output. The example apparatus may further include a wire bond electromagnetic interference cage configured to block the passage of electromagnetic emissions. The wire bond electromagnetic interference cage may include a plurality of bond wires, wherein each bond wire is electrically coupled to an electrical ground, and wherein the wire bond electromagnetic interference cage overlays at least a portion of the target electrical portion. In addition, the wire bond electromagnetic interference cage may further define an electromagnetic interference cage opening through which the optical output passes.

Abstract: An integrated circuit package includes a support substrate having a mounting face and a lateral wall having an inner face and an outer face. The inner face delimits with the mounting face a cavity. The outer face includes a step extending outwardly of the package. An electronic chip disposed in the cavity and electrically connected to electrically-conductive contact pads. A sealing structure is bonded by a glue to an upper face of the lateral wall to seal the cavity. The glue does not spill out over the outer face of the lateral wall. Electrically-conductive connection elements are located over a lower face of the support substrate and electrically cooperate with the contact pads through an interconnection network located in the support substrate.

Abstract: According to an embodiment, a method to mitigate target wraparound in time-of-flight is proposed. The method includes extending the system's pulse interval to include predetermined and dynamic blanking times. The dynamic blanking time is increased by an offset at each successive pulse. The dynamic blanking time is reset in response to reaching a predetermined dynamic blanking time. The dynamic blanking time is initially set to zero. The method further includes processing events within an active window to measure a time interval between the transmission of a pulse and the receipt of a reflected pulse from an object. The duration of the active window is equal to the duration of the initial pulse interval. The method further includes ignoring events within an inactive window, a duration of the inactive window corresponding to the duration of the extended pulse interval minus the duration of the active window.

Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.

Abstract: A system includes at least one first application and a shared software platform. The shared software platform identifies each first application a first random number. The first random number is stored in encrypted fashion in an executable code of the first application. The first application is further identified by a second number which is representative of the first random number. The second number is stored in a first portion of a memory only accessible to the shared software platform.

Abstract: A bridge rectifier circuit and a wireless power receiver configured to receive high voltage AC inputs and generate a stable DC voltage without exposing the bridge rectifier circuitry components to damaging high voltages are provided. The example bridge rectifier includes a plurality of rectifying transistors positioned to generate a DC voltage upon receiving an AC current. The example bridge rectifier circuitry further includes voltage control circuitry designed to output an intermediate voltage to a terminal of one or all of the rectifying transistors of the bridge rectifier. The output intermediate voltage prevents a voltage difference across the terminal of the rectifying transistor from exceeding a maximum voltage rating of the rectifying transistor.

Abstract: A peripheral configured to cooperate with a data processing device including a processor unit is emulated via an emulating peripheral by: emulating data output and data input functions of the peripheral, and emulating data exchange between the peripheral and the processor unit via an emulated replica of a register memory map of the peripheral. The data processing device advantageously includes a Generic Timer Module, GTM with Multi-Channel Sequencer, MCS, and emulation includes: producing, via input and output modules in the GTM, emulating data output and emulating data input functions of the emulating peripheral, wherein the emulating data output and emulating data input functions emulate the data output and data input functions of the peripheral, and producing via the MCS in the GTM an emulated register memory map of the emulating peripheral, wherein the emulated register memory map includes the emulated replica of the register memory map of the peripheral.

Abstract: Data transfer between a master circuit and a slave circuit occurs over an SPI link using five wires. The data are transferred in packets, each packet including a payload and a header specifying the length of the payload. The master circuit defines a number N of bytes to be transferred. During transfer the master determines, after a transfer of N bytes from the master circuit to the slave circuit and of N bytes from the slave circuit to the master circuit, a number of bytes remaining to be transferred from the slave circuit to the master circuit. This determination is made based on a value of the length of the payload included in the header of a data packet transferred from the slave circuit to the master circuit.

Abstract: Disclosed herein is a MEMS device including a frame body, a seismic mass elastically coupled to the frame body, a stopper/sense structure elastically coupled to the frame body. The stopper/sense structure is configured to move with respect to the frame body and to limit the movement of the seismic mass with respect to the frame body or to sense the position of the seismic mass. A stopper/sense actuation group is fixed to the frame body and configured to control the position of the stopper/sense structure in such a way as to vary an adjustable distance between the stopper/sense structure and the seismic mass.