Abstract: According to an embodiment, a method for operating a memory system includes receiving data bits at a memory controller for storage in memory, remapping the data bits according to a predetermined scheme as they are transmitted from the controller to memory via a bus, storing the remapped bits in memory, reading the remapped bits from memory via the bus, and inverse remapping the bits to restore their original order as they are transmitted back to the controller. The remapping enhances fault tolerance by spatially separating related bits. The scheme may use techniques like multiplexing, cyclic shifting, or pseudo-random distribution. The remapping can be implemented through hardwired bus connections without adding clock cycles. The method improves resilience to multi-bit errors in wide-word volatile memories used in safety-critical applications, while maintaining compatibility with existing error detection methods.

Abstract: An amplifier including a first amplification stage unit that includes a first transistor configured to modulate a first transistor threshold voltage using a first control voltage on a body of the first transistor, and a first direct current permitting feedback loop electrically coupling a drain of the first transistor with a gate of the first transistor. The amplifier may include a second amplification stage unit that includes a second transistor configured to modulate a second transistor threshold voltage using a second control voltage on a body of the second transistor, and a second direct current permitting feedback loop electrically coupling a drain of the second transistor with a gate of the second transistor.

Abstract: A time-based DC-DC converter is controlled in response to a first oscillator signal based on a first control signal, a second oscillator signal based on a second control signal and a controlled current based on a feedback control signal. The first control signal and the second control signal are a function of the controlled current. The feedback control signal is generated as a function of the first and second oscillator signals by: generating at least two binary signals including a first binary signal based on a difference between the first oscillator signal and the reference signal and a second binary signal based on a difference between the second oscillator signal and the reference signal; and generating via a charge pump the feedback control signal based on the first binary signal and the second binary signal.

Abstract: An example circuit and an electrical system utilizing test control circuitry to manage the transmission of electrical test signals between an integrated circuit and a main board are provided. The circuit includes test control circuitry configured to selectively transmit electrical test signals between an IC and a pad interface based on a plurality of asynchronous electrical supplies, at least one of which exceeds a maximum voltage rating of the test control circuitry. The test control circuitry includes first and second switching stage circuitry enabling electrical flow through the circuit based on first and second asynchronous electrical supply voltages. Intermediate biasing circuitry further defines an intermediate voltage between the first switching stage circuitry and the second switching stage circuitry.

Abstract: A temperature sensing circuit includes a current generation circuit generating an initial current proportional to absolute temperature (Iptat), and a voltage generation circuit configured to mirror Iptat using an adjustable current source to produce a scaled current and to source the scaled current to a first terminal of a resistor to produce a reference voltage at the first terminal. A second terminal of the resistor has a voltage complementary to absolute temperature (Vctat) applied thereto. An analog-to-digital converter (ADC) has a reference input receiving the reference voltage, and a data input receiving Vctat or an externally sourced voltage. The ADC generates an output code indicative of a ratio between: a) either Vctat or the externally sourced voltage, and b) the reference voltage. A digital circuit determines a temperature readout from the output code and calibrates the reference voltage and the temperature readout determination based upon the output code.

Abstract: An integrated circuit package includes a support substrate with front connection pads on a front surface thereof and rear connection pads on a rear surface thereof. An integrated circuit device is mounted to the support substrate in flip chip orientation with a front face of the integrated circuit device facing the front surface of the support substrate. A thermally conductive heat spreader is mounted adjacent a rear face of the integrated circuit device. External direct thermal paths thermally couple a top surface of the thermally conductive heat spreader to the rear surface of the support substrate. Each external direct thermal path includes a first portion on and in direct contact with thermally conductive heat spreader, a second portion on and in direct contact with an external side surface of the support substrate and a third portion on and in direct contact with the rear surface of the support substrate.

Abstract: A phase-change memory cell to be read is associated with a phase-change reference memory cell placed in a SET state. The reference memory cell has a structure that is identical to that of the memory cell. A first voltage is applied to the memory cell to cause output of a first current. A second voltage is applied to the reference memory cell to cause output of a second current. A sense amplifier is coupled to the memory cell and to the reference memory cell and is configured to compare respective values of the first current and of the second current and generate output information representative of the logic value of the datum stored by the memory cell.

Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry. The convolutional accelerator, in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry, in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.

Abstract: According to an embodiment, a regression analysis is performed on a subset of a dataset, where the subset of the dataset corresponds to inputs from a first row of a matrix of sensors at a time instant k. The regression analysis generates a set of coefficients. A filter transform, to be applied on the subset of the dataset, is determined based on a comparison between the set of coefficients and threshold values. The filter transform can be one of an infinite impulse response (IIR) filter transform, a first-order filter transform, or a second-order filter transform. Once the filter transform is determined, it is applied to the subset of the dataset to generate a first output matrix.

Abstract: A manufacturing method for MEMS devices includes: in a first wafer, forming a MEMS structure; forming a cavity and a blind hole in a first face of a second wafer; on the first face, forming a narrowing structure protruding and interposed between the cavity and the blind hole; and sealing the MEMS structure in a chamber delimited by the cavity. Sealing comprises: joining the second wafer to the first wafer to define fluidic paths between the second wafer and the first wafer and to mutually couple the blind hole and the chamber through the fluidic paths, with the narrowing structure forming a section narrowing in the fluidic paths; forming, in a second face opposite to the first face, at least one access opening, communicating with a respective blind hole, to open a respective chimney and to fluidically couple the chamber to an external environment; and closing the chimney.

Abstract: A microelectromechanical sensor device has a detection structure and an associated electronic circuitry, configured to receive, when the device is powered, an external power supply voltage and provided with a voltage regulator generating a regulated voltage and with at least one voltage domain powered by the regulated voltage. The electronic circuitry has a power supply management core, always powered by the external power supply voltage and which controls the voltage regulator to selectively interrupt the power supply of the voltage domain to implement: a first power-down condition wherein the voltage regulator is disabled; and a second power-down condition wherein the voltage regulator is enabled to power the aforementioned voltage domain through the regulated voltage, the first and the second power-down conditions being associated with absence of data acquisition and/or processing by the sensor device.

Abstract: A process for manufacturing a power electronic device having a plurality of elementary cells, envisages: providing a substrate, having a first electrical conductivity and a first doping value and defining a front surface; forming first CSL – Current Spreading Layer – regions in a deep position of the substrate at a distance from the front surface, having the first electrical conductivity and a second doping value, greater than the first doping value; forming first doped regions of elementary cells of the power electronic device above the first current spreading regions, having a second conductivity type and separated from each other in a direction parallel to the front surface by intercell regions of the power electronic device; forming second CSL – Current Spreading Layer - regions at the intercell regions, having the first electrical conductivity and distinct and independent characteristics with respect to the first current spreading regions.

Abstract: The proposed solution is designed for IGBT and discrete devices with vertical gate; the proposed method includes: trench formation, including lithography and etching, in a wafer; oxidation to grow gate dielectric; polysilicon filling with a thin layer to form first gate conductive layer; a second dielectric deposition and recession to fill half of the trench from the bottom up to a fixed depth; trench filling with polysilicon to form a second gate conductive layer. The second dielectric can be chosen with a dedicated stress and a dedicated recession, to counterbalance the polysilicon stress and reduce wafer warpage.

Abstract: A system and method reliably sort wafers as suitable or unsuitable for processing. A plurality of first test wafers are initially sliced from a semiconductor ingot. A first surface analysis process is performed on each of the first test wafers to generate first surface defect data. A plurality of second test wafers are formed from the first test wafers by bonding the first test wafers to respective substrates. A second surface analysis process is then performed on the second test wafers to generate second surface defect data. A wafer sorting model is generated from the first and second surface defect data. Subsequently, embodiments of the present disclosure utilize the model to sort wafers after performing the first surface analysis process on the wafers.

Abstract: A circuit includes a switching stage with first and second half bridges, each containing a high-side and a low-side DMOS transistor. Output nodes between these transistors supply an electrical load via filter networks. Control circuitry manages switching sequences, alternating pairs of DMOS transistors between conductive and non-conductive states across the half bridges. The circuit features a current flow line with an inductance, connected to two switches that can be set to conductive or non-conductive states. First and second capacitances are coupled to the output nodes of each half bridge. The control circuitry switches the two switches to the conductive state at specific intervals during the switching sequence, based on transitions between transistor pairs. Additionally, control signals for these switches are determined by the delay between output signals at the respective output nodes.

Abstract: A power detector circuit includes a squarer circuit formed by at least one MOSFET device with a gate, a source and a drain. When configured in a normal operating mode, an RF signal and a gate bias signal are applied to the gate of the at least one MOSFET device and a drain current at the drain of the MOSFET device is indicative of power of the RF signal. Conversely, when configured in a calibration mode, a DC test signal and the gate bias signal are applied to the gate of the at least one MOSFET device and the drain current at the drain of the MOSFET device is indicative of power of the DC test signal. The drain current is filtered and converted to analog voltage. The analog voltage is converted to a digital code that is processed to determine a characteristic code of the power detector circuit.

Abstract: Process for manufacturing a microelectromechanical system starting from a first semiconductive wafer including a semiconductive substrate, a semiconductive region, and an interposed dielectric region. The process includes forming first and second cavities in the semiconductive region; forming a first channel through the semiconductive region to the dielectric region, and selectively removing the dielectric region to create an intermediate chamber. The first wafer is coupled to a second semiconductive wafer, where first and second microelectromechanical structures are formed, creating first and second chambers. The second chamber is hermetically closed. A transversal channel connects the first chamber, first channel, and intermediate chamber. Second channels are formed through the substrate to the intermediate chamber, allowing communication with the outside.

Abstract: A synchronization circuit provides bidirectional communication between two clock domains without requiring feedback signals. The circuit includes first and second clock domain circuits, each having a flip-flop with enable control logic and an XOR gate for output generation. In each domain, the output of the flip-flop is inverted and fed back to its input, creating a toggle mechanism controlled by set and clear signals. The XOR gate in each domain compares its local flip-flop state with a synchronized version of the other domain's flip-flop state to generate register output clock signals. Synchronizers or qualified connections between domains ensure reliable cross-domain communication. The circuit maintains operation when either clock stops, preserving state changes for synchronization when clocks resume.

Abstract: A capacitive sensing circuit includes a switched capacitor charge to voltage (C2V) converter circuit having an input coupled to a capacitive sensor and configured to receive a negative feedback signal. An offset and low-frequency noise cancelation circuit has an input coupled to an output of the switched capacitor C2V converter circuit. A sigma-delta analog-to-digital converter (??-ADC) circuit includes a loop filter coupled to an output of the offset and low-frequency noise cancelation circuit, a quantizer coupled to an output of the loop filter and configured to generate a digital signal, and a digital-to-analog converter circuit configured to generate the negative feedback signal from the digital signal.

Abstract: The present disclosure relates to a method for implementing a key-derivation operation of an encryption algorithm. The method is adapted to receive a first key and to generate a second key, the first and second keys each comprising a number N of bytes arranged in an array. First bytes of a byte row of a first rank of the second key are calculated using second bytes of a byte row of the first rank of the first key, and a single third byte of a byte row of a second rank, different from the first rank, of the first key.