Abstract: According to an embodiment, a circuit for detecting faults in a hard disk drive head resistance includes a current digital-to-analog converter generating a scaled current proportional to a write output current through the head resistance. A programmable current mirror with bipolar transistor networks processes the scaled current using parallel-connected scaled replicas of an impedance matching network and a head resistance fault threshold. The current mirror generates mirror currents that flow through matched resistors to create threshold voltages. High-speed comparators with input buffer transistors compare differential voltages from an H-bridge writer output to the threshold voltages while preventing loading effects. A polarity detector maintains fault detection capability regardless of active H-bridge diagonal pairs.

Abstract: The present disclosure relates to an avalanche photodiode pixel including: a transistor adapted to be controlled by an enable signal having a first state for controlling the enabling of the pixel and a second state for controlling the disabling of the pixel, the transistor being configured to couple an avalanche photodiode of the pixel to a node of application of a substrate voltage when the enable signal is in the first state; and an output circuit adapted to be controlled by the enable signal and configured to provide a pixel output signal when the enable signal is in the first state and to block the pixel output signal when the enable signal is in the second state.

Abstract: A method for reading pressure may include reading, by a first device, an acceleration of a pressure sensor, wherein the pressure sensor is encapsulated in a medium, and wherein the acceleration alters a reading of the pressure sensor and reading, by a second device, a pressure reading from the pressure sensor. If an output criteria is met, an adjusted pressure reading is produced. A system for reading pressure includes a first device coupled to the pressure sensor and configured to read an acceleration of the pressure sensor. A second device may be configured to read a pressure from the pressure sensor wherein, if an output criteria is met, to adjust the measured pressure of the pressure sensor, based on the measured acceleration, to produce an adjusted pressure reading. An output device is configured to receive an output of the second device and to output an output pressure reading.

Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.

Abstract: A power detector for detecting the RMS power of an AC voltage includes a transconductor configured to receive the AC voltage and to provide a first current to a node with a non-linear relation between the first current and the voltage. A current output digital to analog converter is configured to receive a digital signal and to provide a second current to the node. A low pass filter is coupled to the node, and an inverter is coupled to the node and configured to provide a binary signal.

Abstract: A coupling and chaining bridge is configured to receive an original data value via a first bus coupled to one of a system bus of an electronic device and a first peripheral circuit of the electronic device. The original data value is transmitted by the coupling and chaining bridge to a second bus of the electronic device coupled to the other of the system bus and the first peripheral circuit. The coupling and chaining bridge is further configured to intercept the original data value and transmit a copy of the original data value to a third bus of the device that is coupled to a second peripheral circuit of the device.

Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.

Abstract: Disclosed herein is a method of forming a thermal sensor, including patterning an active layer on a first face of a handle substrate to form a frame, a mass carrying at least one thermally isolated MOS (TMOS) transistor, and a spring structure connecting the mass to the frame while thermally isolating the mass from the frame. The frame is then bonded to pads on a first face of an integrated circuit substrate. The handle substrate is removed, and a top cap is bonded to the first face of the integrated circuit substrate to enclose at least the mass and spring within the sealed cavity.

Abstract: A method of operating an electronic device includes detecting a plurality of touch inputs for a number of frames on an edge zone of a touchscreen of the device, determining a distance between adjacent touch input within an expanded edge zone, in response to the distance being less than a threshold distance, rejecting the touch inputs as invalid, and in response to the distance being greater than the threshold distance, accepting the touch inputs as valid.

Abstract: According to an embodiment, a method for determining the folding angle of a foldable device is proposed. The device includes a touch controller, a display layer, and a touch-sensing layer. The device is foldable along a folding axis. A first portion is in contact with a second portion of the display layer in a fully closed position of the device. The method includes activating a mutual-capacitance sensing mechanism by configuring one or more channels of the touch-sensing layer parallel to the folding axis on the first portion of the display layer as transmit channels, and configuring one or more channels of the touch-sensing layer parallel to the folding axis on the second portion of the display layer as receive channels; collecting mutual-capacitance raw data measurements; determining the folding angle based on the mutual-capacitance raw data measurements; and activating a function or an application based on the folding angle.

Abstract: A full-bridge class-D amplifier includes: a first branch with a first high-side switch and a first low-side switch coupled at a first output node in series between a supply voltage and ground; and a second branch with a second high-side switch and a second low-side switch coupled at a second output node in series between the supply voltage ground. A circuit for detecting electrical short circuits in the amplifier includes: a measuring circuit configured to provide a first measure of high-side switch operation in one of the branches and a second measure of low-side switch operation in the other of the branches; a checking circuit configured to determine an imbalance between the first and second measures to generate an imbalance signal; and a detection circuit configured to presence of an electrical short circuit in response to the imbalance signal.

Abstract: A DC-DC converter circuit includes: a ramp signal generator circuit; a feedback loop producing a control signal in response to an output voltage of the DC-DC converter circuit; a comparator circuit comparing the control signal to the ramp signal to produce a PWM signal; and a driver stage producing a DC-DC converter circuit power stage switch control signal in response to the PWM signal. A voltage divider produces a feedback voltage indicative of the output voltage of the DC-DC converter circuit. An error amplifier circuit produces an error voltage signal in response to a difference between the feedback voltage and a reference voltage. A filter circuit coupled to the DC-DC converter circuit output produces an AC feedback voltage signal as a function of the output voltage. A voltage adder circuit produces the control signal as a sum of the AC feedback voltage signal and the error voltage signal.

Abstract: A high-side driver-circuit involves a charge-pump for driving a high-side transistor. The circuit includes a high-side transistor, a low-side transistor or unidirectional conducting-device, a bootstrap-capacitor, and a trickle-charge-pump connected between the output-node and ground. The trickle-charge-pump activates when the voltage at the output-node exceeds the voltage at the low-voltage power-supply-node, alternately charging a trickle-capacitor and transferring charge to the bootstrap-capacitor. This enables continuous replenishment of the bootstrap-capacitor, allowing for extended or indefinite high-side conduction periods, including 100% duty-cycle operation. The trickle-charge-pump incorporates an auto-on/auto-off functionality, synchronizing operation with the output-node-voltage.

Abstract: An electronic chip package includes terminals. At least one first terminal of the included terminals is configured to receive and/or deliver a power supply potential. At least one second terminal of the included terminals is configured to receive and/or deliver a reference potential. At least one third terminal of the included terminals is configured to receive and/or deliver a data signal. The at least one third terminal is arranged at the periphery of the package. The at least one first terminal is arranged more centrally in the package than the at least one third terminal.

Abstract: An electronic device includes a non-volatile memory. Operations for reading data from the memory are performed in response to a first clock signal. Operations for writing data to the memory are performed in response to a second clock signal which is different from the first clock signal. The first clock signal is generated by an oscillation circuit of the electronic device, and the second clock signal is generated external to the electronic device (for example through a communications interface).

Abstract: A hypervisor of a virtual machine architecture includes a scheduler module configured to manage execution of commands. The scheduler module operates to: measure an execution time of each command sent to an application in a Secure Element; update a scheduler data structure that stores for each different command, an estimated execution time value (estimated on the basis of measured execution times for the command); store received commands in a queue structure; calculate a remaining time before time out for each command in the queue as a function of a corresponding estimated execution time value obtained from the data structure and a request time out value; execute first the command having the minimum remaining time before time out by sending the command to a Logical Secure Element of the respective application.

Abstract: This disclosure relates to a method for implementing a CBD operation taking as input two first data bits, and providing as output a list of second data bits. The method includes a step A for extracting a first half of bits from the first binary data, a step B for extracting a second half of bits from the first binary data, a step C for summing and masking the data from steps A and B to obtain fifth data and sixth data, a step D for extracting and masking the second data, and a step E for extracting and masking second data, with the order of implementation of steps A, B, C, D, and E being software-controlled.

Abstract: A rectifier includes a first terminal coupled to an output via a component and a second terminal coupled to the output via a component. A transistor has a first node coupled to the first terminal and a second node coupled to a voltage rail. A voltage comparator has an input coupled to the first node of the transistor, an input coupled to the second node of the transistor, and an output coupled to the gate of the transistor. Another transistor has a first node coupled to the second terminal and a second node coupled to the voltage rail. Another voltage comparator has an input coupled to the first node of the other transistor, an input coupled to the second node of the other transistor, and an output coupled to the gate of the other transistor.

Abstract: A semiconductor body has a front side and a back side opposite to each other. A first trench and a second trench are concurrently formed extending through part of the semiconductor body. Each of the first and second trench has respective side walls and a bottom. A first insulation layer having a first thickness is formed at the side walls and the bottom of both the first trench and the second trench. The first insulation layer is then selectively removed from only the second trench. A second insulation layer having a respective second thickness less than the first thickness is formed at the side walls and the bottom of the second trench. The first and second trenches are filled with a conductive material layer.

Abstract: An electronic device includes a Balun-type circuit and a filter circuit configured to generate two phase quadrature signals. The Balun-type circuit includes a primary circuit branch and a secondary circuit branch. The filter circuit is of LC-type and is configured to provide two signals in phase quadrature on first and second nodes. The secondary circuit branch of the Balun-type circuit is connected between the and first and second nodes. An inductor of the primary circuit branch of the Balun-type circuit is magnetically coupled with at least one inductor of the LC-type filter circuit.