Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

Abstract: An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

Abstract: An integrated circuit includes a polysilicon region that is doped with a dopant. A portion of the polysilicon region is converted to a polyoxide region which includes un-oxidized dopant ions. A stack of layers overlies over the polyoxide region. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region. A thermally annealing is performed at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.

Abstract: Disclosed herein is a method of reducing noise captured by an image sensor. The method includes affixing a bottom surface of a glass covering to the image sensor, permitting light to impinge upon the glass covering, and shaping the glass covering such that when the light that impinges upon the glass covering impinges upon a sidewall of the glass covering, the sidewall reflects the light on a trajectory away from the image sensor.

Abstract: A method of manufacturing a chip-sized package includes providing a wafer having a die area formed therein adjacent a front face thereof, with the die area having pads formed thereon. Vias in the wafer are formed to extend between a back face of the wafer and a back side of some of the pads of the die area. Solder pads connected to the vias are formed, and a thermal pad is formed on the back side of the wafer opposite to the die area. Cavities are formed in the back face of the wafer to define pillars extending outwardly from a planar portion of the die area, some of the pillars having the solder pads at a distal end thereof, at least one of the pillars having the thermal pad at a distal end thereof. The wafer is singulated to form a chip-sized package including an integrated circuit die.

Abstract: A digital image sensor package includes an image sensor substrate and a glass covering. The image sensor substrate carries photodiodes. The glass covering has a bottom surface, a top surface opposite the bottom surface, and a sidewall delimiting a perimeter edge of the glass covering. The glass covering overlies the photodiodes. A surface area of the top surface of the glass covering is greater than a surface area of the bottom surface of the glass covering such that the sidewall is anti-perpendicular to the top and bottom surfaces of the glass.

Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.

Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.

Abstract: A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.

Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.

Abstract: The present disclosure is directed to a selective multi-gas sensor device that detects when a high concentration level of a particular gas, such as methane, carbon monoxide, and/or ethanol, is present. The selective multi-gas sensor device detects and identifies a particular gas based on a ratio between a sensitivity of a gas sensitive material at a first temperature and a sensitivity of the gas sensitive material at a second temperature.

Abstract: An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.

Abstract: A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.

Abstract: A gas sensor is formed by a thin-film semiconductor metal-oxide gas sensing layer, with a thermally conductive and electrically-insulating layer in direct physical contact with a back of the gas sensing layer to carry the gas sensing layer. Sensing circuitry applies a voltage to the gas sensing layer and measures a current flowing through the gas sensing layer. The current flowing through the gas sensing layer is indicative of whether a gas under detection has been detected by the gas sensing layer, and serves to self-heat the gas sensing layer. A support structure extends from a substrate to make direct physical contact with and carry the thermally conductive and electrically insulating layer about a perimeter of a back face thereof, with the support structure shaped to form an air gap between the back of the thermally conductive and electrically insulating layer and a front of the substrate.

Abstract: A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.

Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

Abstract: Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.

Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.