Patents Assigned to STMicroelectronics Pte Ltd
  • Patent number: 11908831
    Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics PTE LTD
    Inventors: Chun Yi Teng, David Gani
  • Publication number: 20240036019
    Abstract: The present disclosure is directed to a gas sensor device that detects gases with large molecules (e.g., a gas with a molecular weight between 150 g/mol and 450 g/mol), such as siloxanes. The gas sensor device includes a thin film gas sensor and a bulk film gas sensor. The thin film gas sensor and the bulk film gas sensor each include a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. The SMO film of the thin film gas sensor is an thin film (e.g., between 90 nanometers and 110 nanometers thick), and the SMO film of the bulk film gas sensor is an thick film (e.g., between 5 micrometers and 20 micrometers thick). The gas sensor device detects gases with large molecules based on a variation between resistances of the SMO thin film and the SMO thick film.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS PTE LTD
    Inventors: Malek BRAHEM, Hatem MAJERI, Olivier LE NEEL, Ravi SHANKAR, Enrico Rosario ALESSI, Pasquale BIANCOLILLO
  • Publication number: 20240036169
    Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics PTE LTD
    Inventor: Jing-En LUAN
  • Publication number: 20240030115
    Abstract: The present disclosure is directed to a power package with copper plating terminals. The power package includes at least two terminals coupled to a semiconductor die. An area of a first terminal is greater than an area of a second terminal. The first and second terminals extend to a first and second conductive layers in a backside of the package. A third conductive layer is coupled to a backside surface of the die that is coplanar with the first and second conductive layers. The terminals and conductive layers are copper plating. A first molding compound covers the die and terminals, while a second molding compound fills distances between the die and the extensions of the terminals. The copper plating and the molding compounds enhance the performance of the packaged device in a high-power circuit. In addition, robustness of the package is enhanced compared with conventional packages including wire bonding.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 25, 2024
    Applicant: STMICROELECTRONICS PTE LTD
    Inventor: Loic Pierre Louis RENARD
  • Publication number: 20230411332
    Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 21, 2023
    Applicant: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En LUAN
  • Patent number: 11848378
    Abstract: A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 19, 2023
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Ditto Adnan, Maurizio Gabriele Castorina, Voon Cheng Ngwan, Fadhillawati Tahir
  • Patent number: 11828877
    Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 28, 2023
    Assignee: STMicroelectronics PTE LTD
    Inventor: Jing-En Luan
  • Patent number: 11828875
    Abstract: A semiconductor package that is a proximity sensor includes a light transmitting die, a light receiving die, an ambient light sensor, a cap, and a substrate. The light receiving die and the light transmitting die are coupled to the substrate. The cap is coupled to the substrate forming a first chamber around the light transmitting die and a second chamber around the light receiving die. The cap further includes a recess with contact pads. The ambient light sensor is mounted within the recess of the cap and coupled to the contact pads. The cap includes electrical traces that are coupled to the contact pads within the recess coupling the ambient light sensor to the substrate. By utilizing a cap with a recess containing contact pads, a proximity sensor can be formed in a single semiconductor package all while maintaining a compact size and reducing the manufacturing costs of proximity sensors.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 28, 2023
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: David Gani
  • Patent number: 11821884
    Abstract: The present disclosure is directed to a gas sensor device that detects gases with large molecules (e.g., a gas with a molecular weight between 150 g/mol and 450 g/mol), such as siloxanes. The gas sensor device includes a thin film gas sensor and a bulk film gas sensor. The thin film gas sensor and the bulk film gas sensor each include a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. The SMO film of the thin film gas sensor is an thin film (e.g., between 90 nanometers and 110 nanometers thick), and the SMO film of the bulk film gas sensor is an thick film (e.g., between 5 micrometers and 20 micrometers thick). The gas sensor device detects gases with large molecules based on a variation between resistances of the SMO thin film and the SMO thick film.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: November 21, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS PTE LTD
    Inventors: Malek Brahem, Hatem Majeri, Olivier Le Neel, Ravi Shankar, Enrico Rosario Alessi, Pasquale Biancolillo
  • Patent number: 11808723
    Abstract: The present disclosure is directed to a gas sensor device that includes a plurality of gas sensors. Each of the gas sensors includes a semiconductor metal oxide (SMO) film, a heater, and a temperature sensor. Each of the SMO films is designed to be sensitive to a different gas concentration range. As a result, the gas sensor device is able to obtain accurate readings for a wide range of gas concentration levels. In addition, the gas sensors are selectively activated and deactivated based on a current gas concentration detected by the gas sensor device. Thus, the gas sensor device is able to conserve power as gas sensors are on when appropriate instead of being continuously on.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 7, 2023
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Malek Brahem, Hatem Majeri, Olivier Le Neel, Ravi Shankar
  • Patent number: 11774422
    Abstract: The present disclosure is directed to a selective multi-gas sensor device that detects when a high concentration level of a particular gas, such as methane, carbon monoxide, and/or ethanol, is present. The selective multi-gas sensor device detects and identifies a particular gas based on a ratio between a sensitivity of a gas sensitive material at a first temperature and a sensitivity of the gas sensitive material at a second temperature.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 3, 2023
    Assignee: STMicroelectronics PTE LTD
    Inventors: Fangxing Yuan, Ravi Shankar, Olivier Le Neel
  • Publication number: 20230307302
    Abstract: A semiconductor package includes a silicon substrate with an active surface and an inactive surface. A semiconductor device, such as an image, light, or optical sensor, is formed in the active surface and disposed on the substrate. A glass plate is coupled to the substrate with adhesive. The glass plate includes a sensor area that corresponds to the area of the semiconductor device and holes through the glass plate that are generally positioned around the sensor area of the glass plate. During formation of the package, the holes through the glass plate allow gas released by the adhesive to escape the package and prevent formation of a gas bubble.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 28, 2023
    Applicants: STMICROELECTRONICS LTD, STMICROELECTRONICS PTE LTD
    Inventors: David GANI, Hui-Tzu Wang
  • Patent number: 11742437
    Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP), with a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion having and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to a contact of the die within the package that extends from the transparent substrate to an active surface of the package. The active surface is utilized to mount the package within an electronic device or to a printed circuit board (PCB) accordingly. The package includes a first insulating layer separating the die from the conductive layer, and a second insulating layer on the conductive layer.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 29, 2023
    Assignees: STMICROELECTRONICS LTD, STMICROELECTRONICS PTE LTD
    Inventors: David Gani, Yiying Kuo
  • Publication number: 20230268421
    Abstract: A MOS transistor of vertical-conduction, trench-gate, type, including a first and a second spacer adjacent to portions of a gate oxide of the trench-gate protruding from a semiconductor substrate, the first and second spacers being specular to one another with respect to an axis of symmetry; enriched P+ regions are formed by implanting dopant species within the body regions using the spacers as implant masks. The formation of symmetrical spacers makes it possible to form source, body and body-enriched regions that are auto-aligned with the gate electrode, overcoming the limitations of MOS transistors of the known type in which such regions are formed by means of photolithographic techniques (with a consequent risk of asymmetry).
    Type: Application
    Filed: February 13, 2023
    Publication date: August 24, 2023
    Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS PTE LTD
    Inventors: Vincenzo ENEA, Voon Cheng NGWAN
  • Patent number: 11721657
    Abstract: A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 8, 2023
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En Luan
  • Publication number: 20230245992
    Abstract: An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.
    Type: Application
    Filed: December 14, 2022
    Publication date: August 3, 2023
    Applicant: STMicroelectronics PTE LTD
    Inventor: Jing-En LUAN
  • Publication number: 20230236161
    Abstract: A gas sensor is formed by a thin-film semiconductor metal-oxide gas sensing layer, with a thermally conductive and electrically-insulating layer in direct physical contact with a back of the gas sensing layer to carry the gas sensing layer. Sensing circuitry applies a voltage to the gas sensing layer and measures a current flowing through the gas sensing layer. The current flowing through the gas sensing layer is indicative of whether a gas under detection has been detected by the gas sensing layer, and serves to self-heat the gas sensing layer. A support structure extends from a substrate to make direct physical contact with and carry the thermally conductive and electrically insulating layer about a perimeter of a back face thereof, with the support structure shaped to form an air gap between the back of the thermally conductive and electrically insulating layer and a front of the substrate.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 27, 2023
    Applicants: STMicroelectronics PTE LTD, STMicroelectronics S.r.l.
    Inventors: Ravi SHANKAR, Wei Ren Douglas LEE, Giuseppe BRUNO
  • Publication number: 20230238341
    Abstract: A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.
    Type: Application
    Filed: December 12, 2022
    Publication date: July 27, 2023
    Applicant: STMicroelectronics Pte Ltd
    Inventors: Churn Weng YIM, Maurizio Gabriele CASTORINA, Voon Cheng NGWAN, Yean Ching YONG, Ditto ADNAN, Fadhillawati TAHIR
  • Publication number: 20230230949
    Abstract: A semiconductor package includes a die and a first lamination layer on the die with openings through the first lamination layer. A redistribution layer is on the first lamination layer and extends through the openings to the die. A plurality of conductive extensions are on the redistribution layer with each stud including a first surface on the redistribution layer, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface. A second lamination layer is on the redistribution layer and the first lamination layer with the die encapsulated in molding compound. The second lamination layer is removed around the conductive extensions to expose the second surface and at least a portion of the sidewall of each stud to improve solder bond strength when mounting the package to a circuit board.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 20, 2023
    Applicant: STMICROELECTRONICS PTE LTD
    Inventors: Yong CHEN, David GANI
  • Patent number: 11693149
    Abstract: A method for forming a molded proximity sensor with an optical resin lens and the structure formed thereby. A light sensor chip is placed on a substrate, such as a printed circuit board, and a diode, such as a laser diode, is positioned on top of the light sensor chip and electrically connected to a bonding pad on the light sensor chip. Transparent, optical resin in liquid form is applied as a drop over the light sensor array on the light sensor chip as well as over the light-emitting diode. After the optical resin is cured, a molding compound is applied to an entire assembly, after which the assembly is polished to expose the lenses and have a top surface flush with the top surface of the molding compound.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: July 4, 2023
    Assignees: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMICROELECTRONICS PTE LTD
    Inventors: Wing Shenq Wong, Andy Price, Eric Christison