Patents Assigned to STMicroelectronics Pte Ltd
  • Publication number: 20220368100
    Abstract: An optical sensor package includes an emitter die mounted to an upper surface of a package substrate. A sensor die is mounted to the upper surface of the package substrate using a film on die (FOD) adhesive layer that extends over the upper surface and encapsulates the emitter die. The sensor die is positioned in a stacked relationship with respect to the emitter die such that a light channel region which extends through the sensor die is optically aligned with the emitter die. Light emitted by the emitter die passes through the light channel region of the sensor die. The emitter die and the sensor die are each electrically coupled to the package substrate.
    Type: Application
    Filed: April 4, 2022
    Publication date: November 17, 2022
    Applicant: STMicroelectronics PTE LTD
    Inventor: Loic Pierre Louis RENARD
  • Patent number: 11502192
    Abstract: An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop VfD2 of the monolithic diode device is less than a forward voltage drop VfD1 of the body diode of the MOSFET device. The forward voltage drop VfD2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop VfD2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: November 15, 2022
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Shin Phay Lee, Voon Cheng Ngwan, Maurizio Gabriele Castorina
  • Patent number: 11502029
    Abstract: The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 ?m in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: November 15, 2022
    Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Laurent Herard, David Parker, David Gani
  • Publication number: 20220352133
    Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.
    Type: Application
    Filed: April 6, 2022
    Publication date: November 3, 2022
    Applicant: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En LUAN
  • Publication number: 20220352057
    Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 3, 2022
    Applicants: STMicroelectronics S.r.l., STMicroelectronics Pte Ltd
    Inventors: Roberto TIZIANI, Laurent HERARD
  • Publication number: 20220319963
    Abstract: The present disclosure is directed to embodiments of semiconductor device packages including a plurality of conductive vias and traces formed by an laser-direct structuring process, which includes at least a lasering step and a plating step. First ones of the plurality of conductive vias extend into an encapsulant to contact pads of a die encased within the encapsulant, and second ones of the plurality of conductive vias extend in the encapsulant to end portions of leads in the encapsulant. The second ones of the plurality of conductive vias may couple the leads to contact pads of the die. In some embodiments, the leads of the semiconductor device packages may extend outward and away from encapsulant. In some other alternative embodiments, the leads of the semiconductor device packages may extend outward and away from the encapsulant and then bend back toward the encapsulant such that an end of the lead overlaps a surface of the encapsulant at which the plurality of conductive vias are present.
    Type: Application
    Filed: March 21, 2022
    Publication date: October 6, 2022
    Applicant: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En LUAN
  • Publication number: 20220320332
    Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.
    Type: Application
    Filed: March 14, 2022
    Publication date: October 6, 2022
    Applicant: STMicroelectronics Pte Ltd
    Inventors: Yean Ching YONG, Maurizio Gabriele CASTORINA, Voon Cheng NGWAN, Ditto ADNAN, Fadhillawati TAHIR, Churn Weng YIM
  • Publication number: 20220291277
    Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Applicant: STMicroelectronics Pte Ltd
    Inventors: Pedro Jr Santos PERALTA, David GANI
  • Publication number: 20220285256
    Abstract: A method of forming a wafer-level package includes singulating a wafer into a plurality of reconstituted integrated circuit dice, affixing a carrier to a front side of the plurality of integrated circuit dice, and forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dice, over side edges of the plurality of integrated circuit die, and over adjacent portions of the carrier. Desired areas of the LDS activatable resin are activated to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die.
    Type: Application
    Filed: February 22, 2022
    Publication date: September 8, 2022
    Applicant: STMicroelectronics Pte Ltd
    Inventor: Jing-En LUAN
  • Patent number: 11430765
    Abstract: A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate. The package has a cap coupled to the non-conductive coupling element through ultrasonic plastic welding. The package protects the dice from an outside environment or external stresses or both. A method is desired to form package to reduce glue overflow defects in the package. Fabrication of the package comprises drilling holes in a substrate; forming trenches in the substrate; forming a non-conductive coupling element in the through holes and the trenches to form a locking mechanism; allowing the non-conductive coupling element to harden and cure; coupling a die or dice to the substrate; and coupling a cap to the non-conductive coupling element to protect the die or dice from an outside environment or external stresses or both.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 30, 2022
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jian Zhou
  • Patent number: 11404355
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 2, 2022
    Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Publication number: 20220199582
    Abstract: The present disclosure is directed to a package that includes a plurality of die that are stacked on each other. The plurality of die are within a first resin and conductive layer is on the first resin. The conductive layer is coupled between ones of first conductive vias extending into the first resin to corresponding ones of the plurality of die. The conductive layer and the first conductive vias couple ones of the plurality of die to each other. A second conductive via extends into the first resin to a contact pad of the substrate, and the conductive layer is coupled to the second conductive via coupling ones of the plurality of die to the contact pad of the substrate. A second resin is on and covers the first resin and the conductive layer on the first resin. In some embodiments, the first resin includes a plurality of steps (e.g., a stepped structure). In some embodiments, the first resin includes inclined surfaces (e.g., sloped surfaces).
    Type: Application
    Filed: December 20, 2021
    Publication date: June 23, 2022
    Applicant: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En LUAN
  • Patent number: 11366156
    Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 21, 2022
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Pedro Jr Santos Peralta, David Gani
  • Publication number: 20220189840
    Abstract: An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.
    Type: Application
    Filed: November 3, 2021
    Publication date: June 16, 2022
    Applicant: STMicroelectronics Pte Ltd
    Inventors: Eng Hui GOH, Voon Cheng NGWAN, Fadhillawati TAHIR, Ditto ADNAN, Boon Kiat TUNG, Maurizio Gabriele CASTORINA
  • Publication number: 20220189788
    Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.
    Type: Application
    Filed: October 28, 2021
    Publication date: June 16, 2022
    Applicant: STMicroelectronics Pte Ltd
    Inventor: Jing-En LUAN
  • Publication number: 20220165699
    Abstract: The present disclosure is directed to semiconductor packages that include a molding compound having at least one raised portion that extends outward from the package. In some embodiments, the semiconductor packages have a plurality of raised portions, and a plurality of conductive layers are on the plurality of raised portions. The plurality of raised portions and the plurality of conductive layers are utilized to mount the semiconductor packages to an external electronic device (e.g., a printed circuit board (PCB), another semiconductor package, an external electrical connection, etc.). In some embodiments, the semiconductor packages have a single raised portion with a plurality of conductive layers that are on the single raised portion. The single raised portion and the plurality of conductive layers are utilized to mount the semiconductor packages to the external electronic device.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 26, 2022
    Applicant: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En LUAN
  • Publication number: 20220130750
    Abstract: A method of forming a solder connection includes forming a solder mask on a thermal pad of a printed circuit board. The solder mask leaves unmasked portions of the thermal pad and forming the solder mask includes forming a plurality of mask stripes extending from edges of each unmasked portion towards a center of the unmasked portion. The method includes depositing solder paste on the unmasked portions of the thermal pad and placing an exposed thermal pad of an integrated circuit package on the solder paste deposited on the thermal pad of the printed circuit board. The method includes forming a solder connection by heating the solder paste between the unmasked portions of the thermal pad on the printed circuit board and the exposed thermal pad of the integrated circuit package.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: STMICROELECTRONICS PTE LTD
    Inventors: Daniel YAP, Hung Meng LOH
  • Publication number: 20220122941
    Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.
    Type: Application
    Filed: September 23, 2021
    Publication date: April 21, 2022
    Applicant: STMicroelectronics PTE LTD
    Inventors: Chun Yi TENG, David GANI
  • Publication number: 20220107392
    Abstract: A semiconductor package that is a proximity sensor includes a light transmitting die, a light receiving die, an ambient light sensor, a cap, and a substrate. The light receiving die and the light transmitting die are coupled to the substrate. The cap is coupled to the substrate forming a first chamber around the light transmitting die and a second chamber around the light receiving die. The cap further includes a recess with contact pads. The ambient light sensor is mounted within the recess of the cap and coupled to the contact pads. The cap includes electrical traces that are coupled to the contact pads within the recess coupling the ambient light sensor to the substrate. By utilizing a cap with a recess containing contact pads, a proximity sensor can be formed in a single semiconductor package all while maintaining a compact size and reducing the manufacturing costs of proximity sensors.
    Type: Application
    Filed: December 14, 2021
    Publication date: April 7, 2022
    Applicant: STMICROELECTRONICS PTE LTD
    Inventor: David GANI
  • Patent number: 11270946
    Abstract: The present disclosure is directed to a package that includes openings that extend into the package. The openings are filled with a conductive material to electrically couple a first die in the package to a second die in the package. The conductive material that fills the openings forms electrical interconnection bridges between the first die and the second die. The openings in the package may be formed using a laser and a non-doped molding compound, a doped molding compound, or a combination of doped or non-doped molding compounds.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: March 8, 2022
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yong Chen, David Gani