Patents Assigned to STMicroelectronics Pte Ltd
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Publication number: 20230135000Abstract: A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.Type: ApplicationFiled: October 10, 2022Publication date: May 4, 2023Applicant: STMicroelectronics Pte LtdInventors: Yean Ching YONG, Jianhua JIN, Weiyang YAP, Voon Cheng NGWAN
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Publication number: 20230071048Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Applicant: STMICROELECTRONICS PTE LTDInventors: Jing-En LUAN, Jerome TEYSSEYRE
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Patent number: 11585847Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.Type: GrantFiled: May 27, 2022Date of Patent: February 21, 2023Assignee: STMicroelectronics Pte LtdInventors: Pedro Jr Santos Peralta, David Gani
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Patent number: 11581289Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.Type: GrantFiled: July 21, 2020Date of Patent: February 14, 2023Assignee: STMICROELECTRONICS PTE LTDInventors: Yong Chen, David Gani
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Patent number: 11581232Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.Type: GrantFiled: May 21, 2020Date of Patent: February 14, 2023Assignee: STMICROELECTRONICS PTE LTDInventor: Jing-En Luan
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Patent number: 11581280Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP.Type: GrantFiled: November 25, 2020Date of Patent: February 14, 2023Assignee: STMICROELECTRONICS PTE LTDInventor: David Gani
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Publication number: 20230030627Abstract: Provided is a sensor package with an integrated circuit embedded in a substrate and a sensor die on the substrate. The substrate includes a molding compound that has additives configured to respond to a laser. The integrated circuit is embedded in the molding compound. An opening is through the substrate and is aligned with the sensor die. A lid covers the sensor die and the substrate, forming a cavity. At least one trace is formed on a first surface of the substrate, on an internal sidewall of the opening and on a second surface of the substrate with a laser direct structuring process.Type: ApplicationFiled: July 14, 2022Publication date: February 2, 2023Applicant: STMICROELECTRONICS PTE LTDInventor: Jing-En LUAN
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Publication number: 20230029799Abstract: The present disclosure is directed to embodiments of sensor package including a doped resin on respective surfaces and sidewalls of a transparent portion, a sensor die, and a support structure extending from the transparent portion to the sensor die. The support structure suspends the transparent portion over a sensor of the sensor die. The doped resin is doped with an additive material, and the additive material is activated by exposing the doped resin to a laser. The doped resin is exposed to the laser forming conductive layers extending along the doped resin for providing electrical connections within the sensor package and to electronic components external to the embodiments of the sensor die packages. The conductive layers are at least partially covered by a non-conductive layer.Type: ApplicationFiled: July 26, 2022Publication date: February 2, 2023Applicant: STMICROELECTRONICS PTE LTDInventor: Jing-En LUAN
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Publication number: 20230032887Abstract: Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.Type: ApplicationFiled: July 8, 2022Publication date: February 2, 2023Applicant: STMicroelectronics Pte LtdInventor: Jing-En LUAN
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Patent number: 11562937Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.Type: GrantFiled: January 8, 2021Date of Patent: January 24, 2023Assignee: STMICROELECTRONICS PTE LTDInventors: Yun Liu, David Gani
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Patent number: 11543378Abstract: The present disclosure is directed to a gas sensor that includes an active sensor area that is exposed to an environment for detection of elements. The gas sensor may be an air quality sensor that can be fixed in position or carried by a user. The gas sensor includes a heater formed above chamber. The gas sensor includes an active sensor layer above the heater that forms the active sensor area. The gas sensor can include a passive conductive layer, such as a hotplate that further conducts and distributes heat from the heater to the active sensor area. The heater can include a plurality of extensions. The heater can also include a first conductive layer and a second conductive layer on the first conductive layer where the second conductive layer includes a plurality of openings to increase an amount of heat and to more evenly distribute heat from the heater to the active sensor area.Type: GrantFiled: December 10, 2019Date of Patent: January 3, 2023Assignee: STMICROELECTRONICS PTE LTDInventors: Olivier Le Neel, Alexandre Le Roch, Ayoub Lahlalia, Ravi Shankar
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Patent number: 11527511Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.Type: GrantFiled: November 22, 2019Date of Patent: December 13, 2022Assignees: STMicroelectronics Pte Ltd, STMicroelectronics (Grenoble 2) SASInventors: David Gani, Jean-Michel Riviere
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Publication number: 20220393022Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.Type: ApplicationFiled: April 27, 2022Publication date: December 8, 2022Applicants: STMicroelectronics PTE LTD, STMicroelectronics (Tours) SASInventors: Shin Phay LEE, Voon Cheng NGWAN, Frederic LANOIS, Fadhillawati TAHIR, Ditto ADNAN
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Patent number: 11513220Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.Type: GrantFiled: September 5, 2019Date of Patent: November 29, 2022Assignee: STMICROELECTRONICS PTE LTDInventors: Jing-En Luan, Jerome Teysseyre
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Publication number: 20220368100Abstract: An optical sensor package includes an emitter die mounted to an upper surface of a package substrate. A sensor die is mounted to the upper surface of the package substrate using a film on die (FOD) adhesive layer that extends over the upper surface and encapsulates the emitter die. The sensor die is positioned in a stacked relationship with respect to the emitter die such that a light channel region which extends through the sensor die is optically aligned with the emitter die. Light emitted by the emitter die passes through the light channel region of the sensor die. The emitter die and the sensor die are each electrically coupled to the package substrate.Type: ApplicationFiled: April 4, 2022Publication date: November 17, 2022Applicant: STMicroelectronics PTE LTDInventor: Loic Pierre Louis RENARD
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Patent number: 11502029Abstract: The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 ?m in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.Type: GrantFiled: July 13, 2020Date of Patent: November 15, 2022Assignees: STMICROELECTRONICS PTE LTD, STMICROELECTRONICS (ROUSSET) SASInventors: Laurent Herard, David Parker, David Gani
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Patent number: 11502192Abstract: An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop VfD2 of the monolithic diode device is less than a forward voltage drop VfD1 of the body diode of the MOSFET device. The forward voltage drop VfD2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop VfD2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.Type: GrantFiled: March 30, 2021Date of Patent: November 15, 2022Assignee: STMicroelectronics Pte LtdInventors: Shin Phay Lee, Voon Cheng Ngwan, Maurizio Gabriele Castorina
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Publication number: 20220352057Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.Type: ApplicationFiled: April 26, 2022Publication date: November 3, 2022Applicants: STMicroelectronics S.r.l., STMicroelectronics Pte LtdInventors: Roberto TIZIANI, Laurent HERARD
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Publication number: 20220352133Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.Type: ApplicationFiled: April 6, 2022Publication date: November 3, 2022Applicant: STMICROELECTRONICS PTE LTDInventor: Jing-En LUAN
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Publication number: 20220319963Abstract: The present disclosure is directed to embodiments of semiconductor device packages including a plurality of conductive vias and traces formed by an laser-direct structuring process, which includes at least a lasering step and a plating step. First ones of the plurality of conductive vias extend into an encapsulant to contact pads of a die encased within the encapsulant, and second ones of the plurality of conductive vias extend in the encapsulant to end portions of leads in the encapsulant. The second ones of the plurality of conductive vias may couple the leads to contact pads of the die. In some embodiments, the leads of the semiconductor device packages may extend outward and away from encapsulant. In some other alternative embodiments, the leads of the semiconductor device packages may extend outward and away from the encapsulant and then bend back toward the encapsulant such that an end of the lead overlaps a surface of the encapsulant at which the plurality of conductive vias are present.Type: ApplicationFiled: March 21, 2022Publication date: October 6, 2022Applicant: STMICROELECTRONICS PTE LTDInventor: Jing-En LUAN