Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.

Abstract: An optical sensor package includes an emitter die mounted to an upper surface of a package substrate. A sensor die is mounted to the upper surface of the package substrate using a film on die (FOD) adhesive layer that extends over the upper surface and encapsulates the emitter die. The sensor die is positioned in a stacked relationship with respect to the emitter die such that a light channel region which extends through the sensor die is optically aligned with the emitter die. Light emitted by the emitter die passes through the light channel region of the sensor die. The emitter die and the sensor die are each electrically coupled to the package substrate.

Abstract: An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop VfD2 of the monolithic diode device is less than a forward voltage drop VfD1 of the body diode of the MOSFET device. The forward voltage drop VfD2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop VfD2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.

Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

Abstract: A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

Abstract: A method of forming a wafer-level package includes singulating a wafer into a plurality of reconstituted integrated circuit dice, affixing a carrier to a front side of the plurality of integrated circuit dice, and forming a laser direct structuring (LDS) activatable resin over a back side of the plurality of integrated circuit dice, over side edges of the plurality of integrated circuit die, and over adjacent portions of the carrier. Desired areas of the LDS activatable resin are activated to form conductive areas within the LDS activatable resin, at least one of the conductive areas associated with each integrated circuit die being formed to contact a respective a respective pad of that integrated circuit die and to run alongside to and in contact with a side of the LDS activatable resin in contact with a side edge of that integrated circuit die.

Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

Abstract: An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

Abstract: A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.

Abstract: A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.

Abstract: A compact microelectronic gas sensor module includes electrical contacts formed in such a way that they do not consume real estate on an integrated circuit chip. Using such a design, the package can be miniaturized further. The gas sensor is packaged together with a custom-designed Application Specific Integrated Circuit (ASIC) that provides circuitry for processing sensor signals to identify gas species within a sample under test. In one example, the output signal strength of the sensor is enhanced by providing an additional metal surface area in the form of pillars exposed to an electrolytic gas sensing compound, while reducing the overall package size. In some examples, bottom side contacts are formed on the underside of the substrate on which the gas sensor is formed. Sensor electrodes may be electrically coupled to the ASIC directly, or indirectly by vias.

Abstract: A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.

Abstract: A digital image sensor package includes an image sensor substrate and a glass covering. The image sensor substrate carries photodiodes. The glass covering has a bottom surface, a top surface opposite the bottom surface, and a sidewall delimiting a perimeter edge of the glass covering. The glass covering overlies the photodiodes. A surface area of the top surface of the glass covering is greater than a surface area of the bottom surface of the glass covering such that the sidewall is anti-perpendicular to the top and bottom surfaces of the glass.

Abstract: One or more embodiments are directed to ambient light sensor packages, and methods of making ambient light sensor packages. One embodiment is directed to an ambient light sensor package that includes an ambient light sensor die having opposing first and second surfaces, a light sensor on the first surface of the ambient light sensor die, one or more conductive bumps on the second surface of the ambient light sensor die, and a light shielding layer on at least the first surface and the second surface of the ambient light sensor die. The light shielding layer defines an opening over the light sensor. The ambient light sensor package may further include a transparent cover between the first surface of the ambient light sensor die and the light shielding layer, and an adhesive that secures the transparent cover to the ambient light sensor die.

Abstract: An integrated circuit includes a polysilicon region that is doped with a dopant. A portion of the polysilicon region is converted to a polyoxide region which includes un-oxidized dopant ions. A stack of layers overlies over the polyoxide region. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region. A thermally annealing is performed at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.

Abstract: An integrated circuit includes a MOSFET device and a monolithic diode device, wherein the monolithic diode device is electrically connected in parallel with a body diode of the MOSFET device. The monolithic diode device is configured so that a forward voltage drop VfD2 of the monolithic diode device is less than a forward voltage drop VfD1 of the body diode of the MOSFET device. The forward voltage drop VfD2 is process tunable by controlling a gate oxide thickness, a channel length and body doping concentration level. The tunability of the forward voltage drop VfD2 advantageously permits design of the integrated circuit to suit a wide range of applications according to requirements of switching speed and efficiency.

Abstract: A blind opening is formed in a bottom surface of a semiconductor substrate to define a thin membrane suspended from a substrate frame. The thin membrane has a topside surface and a bottomside surface. A stress structure is mounted to one of the topside surface or bottomside surface of the thin membrane. The stress structure induces a bending of the thin membrane which defines a normal state for the thin membrane. Piezoresistors are supported by the thin membrane. In response to an applied pressure, the thin membrane is bent away from the normal state and a change in resistance of the piezoresistors is indicative of the applied pressure.

Abstract: A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.